An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas comprising carbon at a constant RF power level. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.

Plasma processes for depositing low dielectric constant films

A faceplate for a showerhead of a semiconductor wafer processing system is provided. The faceplate has a plurality of gas passageways to provide a plurality of gases to the process region without commingling those gases before they reach the processing region within a reaction chamber. The showerhead includes a faceplate and a gas distribution manifold assembly. The faceplate defines a plurality of first gas holes that carry a first gas from the manifold assembly through the faceplate to the process region, and a plurality of channels that couple a plurality of second gas holes to a radial plenum that receives the second gas from the manifold assembly. The faceplate and the manifold assembly are each fabricated from a substantially solid nickel material.

Dual gas faceplate for a showerhead in a semiconductor wafer processing system

An interferometric modulator manufactured according to a particular set of processing parameters may have a non-zero offset voltage. A process has been developed for modifying the processing parameters to shift the non-zero offset voltage closer to zero. For example, the process may involve identifying a set of processing parameters for manufacturing an interferometric modulator that results in a non-zero offset voltage for the interferometric modulator. The set of processing parameters may then be modified to shift the non-zero offset voltage closer to zero. For example, modifying the set of processing parameters may involve modifying one or more deposition parameters used to make the interferometric modulator, applying a current (e.g., a counteracting current) to the interferometric modulator, and/or annealing the interferometric modulator. Interferometric modulators made according to the set of modified processing parameters may have improved performance and/or simpler drive schemes.

Process for modifying offset voltage characteristics of an interferometric modulator

A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects

Integrated low k dielectrics and etch stops

A dielectric etch process particularly applicable to forming a dual-damascene interconnect structure by a counterbore process, in which a deep via is etched prior to the formation of a trench connecting two of more vias. A single metallization fills the dual-damascene structure. The substrate is formed with a lower stop layer, a lower dielectric layer, an upper stop layer, and an upper dielectric layer. For example, the dielectric layers may be silicon dioxide, and the stop layers, silicon nitride. The initial deep via etch includes at least two substeps. A first substep includes a non-selective etch through the upper stop layer followed by a second substep of selectively etching through the lower dielectric layer and stopping on the lower stop layer. The first substep may be preceded by yet another substep including a selective etch part ways through the upper dielectric layer. For the oxide/nitride compositions, the selective etch is based on a fluorocarbon and argon chemistry, preferably with a lean etchant of CHF3 combined with a polymer former, such as C2F6, C4F8, or CH2F2, and the non-selective etch includes a fluorocarbon or hydrocarbon, argon and an oxygen-containing gas, such as CO. The counterbore etch is preferably performed in a high-density plasma reactor which allows the plasma source region to be powered separately from a sheath bias located adjacent to the wafer pedestal.

Counterbore dielectric plasma etch process particularly useful for dual damascene

A dielectric etch process applicable etching a dielectric layer with an underlying stop layer. It is particularly though not necessarily applicable to forming a dual-damascene interconnect structure by a counterbore process, in which a deep via is etched prior to the formation of a trench connecting two of more vias. A single metallization fills the dual-damascene structure. The substrate is formed with a lower stop layer, a lower dielectric layer, an upper stop layer, and an upper dielectric layer. For example, the dielectric layers may be silicon dioxide, and the stop layers, silicon nitride. The initial deep via etch includes at least two substeps. A first substep includes a non-selective etch through the upper stop layer followed by a second substep of selectively etching through the lower dielectric layer and stopping on the lower stop layer. The first substep may be preceded by yet another substep including a selective etch part ways through the upper dielectric layer. For the oxide/nitride compositions, the selective etch is based on a fluorocarbon and argon chemistry, preferably with a lean etchant of CHF3 combined with a polymer former, such as C2F6, C4F8, or CH2F2, and the non-selective etch includes a fluorocarbon or hydrocarbon, argon and an oxygen-containing gas, such as CO. The counterbore etch is preferably performed in a high-density plasma reactor which allows the plasma source region to be powered separately from a sheath bias located adjacent to the wafer pedestal.

Plasma etch process in a single inter-level dielectric etch

A method of depositing and etching dielectric layers having low dielectric constants
and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount
of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to
provide low k dielectric layers that can replace etch stop layers or conventional dielectric
layers in damascene applications. A dual damascene structure having two or more dielectric
layers with dielectric constants lower than about 4 can be deposited in a single reactor and
then etched to form vertical and horizontal interconnects by varying the concentration of a
carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical
interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded
from etch gases for forming horizontal interconnects.

Method of depositing and etching dielectric layers

The introduction of copper interconnects into integrated circuits has increased the use of dual damascene dielectric etch applications because copper films are difficult to plasma etch. Fencing and faceting around the via hole during the trench etch of the via-first dual damascene integration scheme are particularly detrimental and can lead to problems during copper metallization and ultimately to device failure. Therefore, it is imperative that the evolution of these features be understood so that they can be avoided. In this article we will begin with an overview of the via-first dual damascene integration scheme. Experimental results will then be presented that indicate the evolution of these features is heavily dependent upon the existing via profile and whether bottom antireflection coating and/or photoresist is in the via hole prior to starting the trench etch. An empirical model for fence formation was then confirmed by a simple profile simulator written in Visual Basic. Finally, several options for avoiding the evolution of fencing and faceting during the trench etch will be proposed.

Betty Tang

Papers

Integrated low k dielectrics and etch stops

Counterbore dielectric plasma etch process particularly useful for dual damascene

Plasma etch process in a single inter-level dielectric etch

Method of depositing and etching dielectric layers

Understanding the evolution of trench profiles in the via-first dual damascene integration scheme