Bijoy Kundu

Bio: Bijoy Kundu is an academic researcher from Indian Institute of Engineering Science and Technology, Shibpur. The author has contributed to research in topics: Serial binary adder & Encoder. The author has an hindex of 2, co-authored 2 publications receiving 166 citations.

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

Abstract: In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 $\mu $ W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 $\mu $ W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79- $\mu $ W (53.36- $\mu $ W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

Design and implementation of fast FPGA based architecture for reversible watermarking

Abstract: There are diverse hardware realization for digital watermarking of multimedia proposed in the literature. This paper focuses on the design and implementation of a fast FPGA(Field Programmable Gate Array) based architecture using reversible contrast mapping (RCM) based image watermarking algorithm. The specialty of this architecture attracts to the fact of clock-less encoder design and implementation which makes the design faster. The encoder module response time is independent of clock frequency, so the embedding of the watermark is possible as soon as the input is fetched. The schematic based design and implementation of the VLSI architecture have been done with Xilinx 14.1 on Spartan 3E FPGA family. The encoder requires 528 4-input LUTs and 303 slices. On the contrary, the decoder requires 613 LUTs and 347 slices. The maximum clock frequency of the decoder is 45 MHz. The results show the viability of low cost, high speed realtime use of the proposed VLSI architecture.

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

Abstract: In this paper, novel circuits for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. We also propose six new hybrid 1-bit full-adder (FA) circuits based on the novel full-swing XOR–XNOR or XOR/XNOR gates. Each of the proposed circuits has its own merits in terms of speed, power consumption, power-delay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive HSPICE and Cadence Virtuoso simulations are performed. The simulation results, based on the 65-nm CMOS process technology model, indicate that the proposed designs have superior speed and power against other FA designs. A new transistor sizing method is presented to optimize the PDP of the circuits. In the proposed method, the numerical computation particle swarm optimization algorithm is used to achieve the desired value for optimum PDP with fewer iterations. The proposed circuits are investigated in terms of variations of the supply and threshold voltages, output capacitance, input noise immunity, and the size of transistors.

Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation

Abstract: A novel design of a hybrid Full Adder (FA) using Pass Transistors (PTs), Transmission Gates (TGs) and Conventional Complementary Metal Oxide Semiconductor (CCMOS) logic is presented. Performance analysis of the circuit has been conducted using Cadence toolset. For comparative analysis, the performance parameters have been compared with twenty existing FA circuits. The proposed FA has also been extended up to a word length of 64 bits in order to test its scalability. Only the proposed FA and five of the existing designs have the ability to operate without utilizing buffer in intermediate stages while extended to 64 bits. According to simulation results, the proposed design demonstrates notable performance in power consumption and delay which accounted for low power delay product. Based on the simulation results, it can be stated that the proposed hybrid FA circuit is an attractive alternative in the data path design of modern high-speed Central Processing Units.

Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology

Abstract: In this paper, a number of novel 1-bit full adder cells using carbon nanotube field-effect transistor devices are presented. First of all, some two-input XOR/XNOR circuits are proposed, and then, they are employed to form 1-bit full adders. Totally, five full adders with driving power and one without driving power are proposed in this paper, each of which has its own merits. Simulations with regard to supply power scaling and different load conditions confirm the superiority of the proposed cells compared with the previously reported ones in terms of power, delay, power-delay product (PDP), and Energy-delay product (EDP). Also embedding the proposed full adders in the large circuits,such as ripple carry adder (RCA), with a wide word length shows that they have better power, speed, and PDP with regard to their counterparts. Furthermore, the susceptibility of the full adders against both input noise and process variations (diameter deviations of carbon nanotubes) is studied. In terms of noise, the proposed cells have a close competition to their counterparts, and they are robust against high amplitude of noises. In terms of process variation, the proposed cells with driving power display the most robustness compared with their counterpart.