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Bin Gao

Researcher at Tsinghua University

Publications -  349
Citations -  12155

Bin Gao is an academic researcher from Tsinghua University. The author has contributed to research in topics: Resistive random-access memory & Neuromorphic engineering. The author has an hindex of 45, co-authored 299 publications receiving 8077 citations. Previous affiliations of Bin Gao include Peking University & Stanford University.

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Fully hardware-implemented memristor convolutional neural network

TL;DR: The fabrication of high-yield, high-performance and uniform memristor crossbar arrays for the implementation of CNNs and an effective hybrid-training method to adapt to device imperfections and improve the overall system performance are proposed.
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Face classification using electronic synapses

TL;DR: An analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials is presented and shows bidirectional continuous weight modulation behaviour, consolidating the feasibility of analogue synaptic array and paving the way toward building an energy efficient and large-scale neuromorphic system.
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A Low Energy Oxide‐Based Electronic Synaptic Device for Neuromorphic Visual Systems with Tolerance to Device Variation

TL;DR: The performance of an artificial visual system on the image orientation or edge detection with 16 348 oxide-based synaptic devices is simulated, successfully demonstrating a key feature of neuromorphic computing: tolerance to device variation.
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Bridging Biological and Artificial Neural Networks with Emerging Neuromorphic Devices: Fundamentals, Progress, and Challenges.

TL;DR: A systematic overview of biological and artificial neural systems is given, along with their related critical mechanisms, and the existing challenges are highlighted to hopefully shed light on future research directions.
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Neuro-inspired computing chips

TL;DR: The development of neuro-inspired computing chips and their key benchmarking metrics are reviewed, providing a co-design tool chain and proposing a roadmap for future large-scale chips are provided and a future electronic design automation tool chain is proposed.