We report a high-performance normally-off Al2O3/AlN/GaN MOS-channel-high electron mobility transistor (MOSC-HEMT) featuring a monocrystalline AlN interfacial layer inserted between the amorphous Al2O3 gate dielectric and the GaN channel. The AlN interfacial layer effectively blocks oxygen from the GaN surface and prevents the formation of detrimental Ga-O bonds. Frequency-dispersion in C-V characteristics and threshold voltage hysteresis are effectively suppressed, owing to improved interface quality. The new MOSC-HEMTs exhibit a maximum drain current of 660 mA/mm, a field-effect mobility of 165 cm2/V·s, a high on/off drain current ratio of ~1010, and low dynamic on-resistance degradation.

Interface Characterization of Normally-Off Al2O3/AlN/GaN MOS-Channel-HEMTs with an AlN Interfacial Layer

This study presents the characteristics of HfAlO films for a series of Al incorporation ratios into a HfO2 dielectric by atomic layer deposition on a Si substrate. A small amount of Al doping into the HfO2 film can stabilize the tetragonal phase of the HfO2, which helps to achieve a higher dielectric constant (k) and lower leakage current density, as well as a higher breakdown voltage than HfO2 film on its own. Moreover, assimilation of Al2O3 into HfO2 can reduce the hysteresis width and frequency dispersion. These are indications of border trap reduction, which was also verified by the border trap extraction mechanism. X-ray photoelectron spectroscopy (XPS) analysis also verified the HfAlO microstructural properties for various Al compositions. In addition, higher amounts of Al2O3 in HfAlO resulted in better interface and dielectric behavior through trap minimization, although the equivalent-oxide-thickness (EOT) values show the opposite trend.

https://www.mdpi.com/2072-666X/10/6/361/pdf

Characterization of Al Incorporation into HfO2 Dielectric by Atomic Layer Deposition.

Effect of different Na supply methods on thin Cu(In,Ga)Se2 solar cells with Al2O3 rear passivation layers

Si-based group III-V material enables a multitude of applications and functionalities of the novel optoelectronic integration chips (OEICs) owing to their excellent optoelectronic properties and compatibility with the mature Si CMOS process technology. To achieve high performance OEICs, the crystal quality of the group III-V epitaxial layer plays an extremely vital role. However, there are several challenges for high quality group III-V material growth on Si, such as a large lattice mismatch, highly thermal expansion coefficient difference, and huge dissimilarity between group III-V material and Si, which inevitably leads to the formation of high threading dislocation densities (TDDs) and anti-phase boundaries (APBs). In view of the above-mentioned growth problems, this review details the defects formation and defects suppression methods to grow III-V materials on Si substrate (such as GaAs and InP), so as to give readers a full understanding on the group III-V hetero-epitaxial growth on Si substrates. Based on the previous literature investigation, two main concepts (global growth and selective epitaxial growth (SEG)) were proposed. Besides, we highlight the advanced technologies, such as the miscut substrate, multi-type buffer layer, strain superlattice (SLs), and epitaxial lateral overgrowth (ELO), to decrease the TDDs and APBs. To achieve high performance OEICs, the growth strategy and development trend for group III-V material on Si platform were also emphasized.

/pdf/review-of-highly-mismatched-iii-v-heteroepitaxy-growth-on-2mi0hj90.pdf

Review of Highly Mismatched III-V Heteroepitaxy Growth on (001) Silicon

An analytical modeling of charge plasma based Tunnel Field Effect Transistor with impacts of gate underlap region

Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate–drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.

A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution

GeSn alloys have already attracted extensive attention due to their excellent properties and wide-ranging electronic and optoelectronic applications. Both theoretical and experimental results have shown that direct bandgap GeSn alloys are preferable for Si-based, high-efficiency light source applications. For the abovementioned purposes, molecular beam epitaxy (MBE), physical vapour deposition (PVD), and chemical vapor deposition (CVD) technologies have been extensively explored to grow high-quality GeSn alloys. However, CVD is the dominant growth method in the industry, and it is therefore more easily transferred. This review is focused on the recent progress in GeSn CVD growth (including ion implantation, in situ doping technology, and ohmic contacts), GeSn detectors, GeSn lasers, and GeSn transistors. These review results will provide huge advancements for the research and development of high-performance electronic and optoelectronic devices.

Review of Si-Based GeSn CVD Growth and Optoelectronic Applications

Based on an analytical surface potential model incorporating the channel inversion carriers, a physics-based terminal capacitance model with closed-form solutions for a hetero-gate-dielectric (HGD) tunnel field-effect transistor (TFET) is developed for the first time. Good agreements between the proposed model and the numerical simulations have been achieved in all operation regimes and for different HGD structures. The developed model without involving any iterative process can be easily applied to the widely used SPICE simulations and would be helpful for the transient performance of TFET-based circuits.

Fully Analytical Carrier-Based Charge and Capacitance Model for Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

In this paper, a universal analytical current model for a double-gate Si-based tunnel field-effect transistor (TFET) is presented considering the effects of charges in source depletion region and channel. An accurate surface potential model is developed first by solving the pseudo-2-D Poisson equations in the depletion regions, and then is used to calculate the drain tunneling current. The modeling results match well with that obtained from the Technology computer-aided design simulations under various biasing conditions, which indicate that the analytical current model would be very helpful for the further TFET-based circuits design. Furthermore, the influence of the source depletion is also studied, and the presented model with considering the source depletion region and the channel inversion charges is proved to be much more accurate than that ignoring the source depletion.

A Fully Analytical Current Model for Tunnel Field-Effect Transistors Considering the Effects of Source Depletion and Channel Charges

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.

Bin Lu

Papers

A Charge-Based Capacitance Model for Double-Gate Tunnel FETs With Closed-Form Solution

Review of Si-Based GeSn CVD Growth and Optoelectronic Applications

Fully Analytical Carrier-Based Charge and Capacitance Model for Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

A Fully Analytical Current Model for Tunnel Field-Effect Transistors Considering the Effects of Source Depletion and Channel Charges

Drain Current Model for Double Gate Tunnel-FETs with InAs/Si Heterojunction and Source-Pocket Architecture