This literature review presents the History, Technology, and Applications of Natural Dialog Systems or simply chatbots. It aims to organize critical information that is a necessary background for further research activity in the field of chatbots. More specifically, while giving the historical evolution, from the generative idea to the present day, we point out possible weaknesses of each stage. After we present a complete categorization system, we analyze the two essential implementation technologies, namely, the pattern matching approach and machine learning. Moreover, we compose a general architectural design that gathers critical details, and we highlight crucial issues to take into account before system design. Furthermore, we present chatbots applications and industrial use cases while we point out the risks of using chatbots and suggest ways to mitigate them. Finally, we conclude by stating our view regarding the direction of technology so that chatbots will become really smart.

Chatbots: History, technology, and applications

The use of chatbots evolved rapidly in numerous fields in recent years, including Marketing, Supporting Systems, Education, Health Care, Cultural Heritage, and Entertainment. In this paper, we first present a historical overview of the evolution of the international community’s interest in chatbots. Next, we discuss the motivations that drive the use of chatbots, and we clarify chatbots’ usefulness in a variety of areas. Moreover, we highlight the impact of social stereotypes on chatbots design. After clarifying necessary technological concepts, we move on to a chatbot classification based on various criteria, such as the area of knowledge they refer to, the need they serve and others. Furthermore, we present the general architecture of modern chatbots while also mentioning the main platforms for their creation. Our engagement with the subject so far, reassures us of the prospects of chatbots and encourages us to study them in greater extent and depth.

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An Overview of Chatbot Technology

Deep-ocean polymetallic nodules form on or just below the vast, sediment-covered, abyssal plains of the global ocean. Polymetallic nodules primarily consist of precipitated iron oxyhydroxides and manganese oxides, onto which metals such as nickel, cobalt, copper, titanium and rare earth elements sorb. The enormous tonnage of nodules on the seabed, and the immense quantities of critical metals that they contain, have made them a target for future mining operations. Mining of polymetallic nodules has been spurred by the need for critical metals to support growing populations, urbanization, high-technology applications and the development of a green-energy economy. Nevertheless, an improved understanding of the affected ecosystems and their connectivity, as well as the environmental impacts of deep-ocean mining, is required before operations begin. Opportunities exist, however, to ensure that this new industry applies adaptive management to continually refine operations with the goal of environmental protection and invests in the development of green technologies for extractive metallurgy and mining. In this Review, we explore the chemical processes that control the concentration of critical metals in deep-ocean polymetallic nodules, discuss the mining and metallurgical techniques required, and highlight the opportunities and potential risks that are presented by this new industry. Deep-ocean polymetallic nodules contain an enormous tonnage of critical metals, which are vital natural resources for green-energy technologies and vehicles. This Review highlights the formation processes of these nodules and outlines the advantages and disadvantages for this developing industry moving forward.

Deep-ocean polymetallic nodules as a resource for critical materials

Preface. Glossary. 1. Introduction to FPGAs. 2. Commercially Available FPGAs. 3. Technology Mapping for FPGAs. 4. Logic Block Architecture. 5. Routing for FPGAs. 6. Flexibility of FPGA Routing Architectures. 7. A Theoretical Model for FPGA Routing. References. Index.

Field-Programmable Gate Arrays

The nonstationary and multicomponent nature of newborn EEG seizures tends to increase the complexity of the seizure detection problem. In dealing with this type of problems, time-frequency-based techniques were shown to outperform classical techniques. This paper presents a new time-frequency-based EEG seizure detection technique. The technique uses an estimate of the distribution function of the singular vectors associated with the time-frequency distribution of an EEG epoch to characterise the patterns embedded in the signal. The estimated distribution functions related to seizure and nonseizure epochs were used to train a neural network to discriminate between seizure and nonseizure patterns.

Time-Frequency Feature Extraction of Newborne EEG Seizure using SVD-Based Techniques

Artificial Intelligence in machines is a very challenging discussion. It involves the creation of machines which can simulate intelligence. This paper discusses some of the current trends and practices in AI and subsequently offers alternative theory for improvement in some of today’s prominent and widely accepted postulates. For this, focus on the structuring and functioning of a simple A.I. system chatbots (or chatter bots) is made. The paper shows how current approach towards A.I. is not adequate and offers a new theory that discusses machine intelligence, throwing light to the future of intelligent systems.

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A Study of Today's A.I. through Chatbots and Rediscovery of Machine Intelligence

In this work, we are making energy efficient ALU using the most energy efficient LVCMOS IO standard for the highest frequency of i7 processor. It is observed that LVCMOS12 is the most energy efficient than all available LVCMOS having 26.23, 58.37 and 75.65 % less IO power reduction than LVCMOS18, LVCMOS25 and LVCMOS33 respectively at 1 GHz. Then we are making this ALU portable using MOBILE DDR IO standard in place of default LVCMOS33 IO standard which we use in traditional ALU. As we replace LVCMOS with MOBILE DDR, we are achieving 69.07 % portability in terms of IO power and 29.36 % in terms of Leakage power at 2.9 GHz. In next stage, we try to enhance the performance of ALU with MOBILE DDR but not beyond the power consumption with LVCMOS. In that way, we achieve the highest frequency of 12 GHz with MOBILE DDR. That was earlier possible for 3.8 GHz 64-bit ALU using CMOS. In this HDL based implementation of 64-bit ALU on FPGA, Kintex-7 FPGA is used with XC7K70T device and FBG676 package is used.

Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA

In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and 55.78% of total dynamic power when device operating frequency is 100MHz, 1GHz, 10GHz, 100GHz and 1 THz. After implementation of clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total dynamic power, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz. On 1 THz operating frequency, when we use clock gating, there are 72.77% reduction in clock power, 38.88% reduction in IOs power and 44% reduction in dynamic power in compare to power consumption without using clock gating techniques. Target device is 90-nm Spartan-3. There is 14.57% reduction in junction temperature on 10GHz operating frequency in compare to temperature without using clock gating techniques. Clock gating saves power but increases over all area. There is 32.35%, 37.84%, 43.31% and 44% reduction in dynamic current when we use clock gate on 1GHz, 10GHz, 100GHz and 1THz operating frequency respectively.

Clock gating based energy efficient ALU design and implementation on FPGA

Image ALU is a special type of ALU exclusively designed to perform arithmetic and logical operation on Image only. This Image ALU design is able to perform 14 operations. In this work, we have proposed a novel 4-stages energy efficient CTHS (C-Capacitance Scaling, T-Thermal Scaling, H-HSTL I/O Standard, S-SSTL I/O Standard) approach for Low Power and Thermal Aware Image ALU Design. CTHS technique is achieving 81.79 % reduction in power consumption which is more than the power reduction by method discussed in Shrivastava et al. (IEEE Trans Very Large Scale Integr Syst 18(6):988---997, 2010); Yoonjin and Mahapatra (IEEE Trans Very Large Scale Integr Syst 18(1):15---28, 2010); Chatterjee and Sachdev (IEEE Trans Very Large Scale Integr Syst 13(11):1296---1304, 2005); Wijeratne et al. (IEEE J Solid State Circuits 42(1):26---37, 2007); Nehru et al. (International conference on advances in engineering, science and management pp 145---149, 2012); Ho et al. (IEEE international symposium on circuits and systems pp 353---356, 2013); Rani et al. (3rd in international conference on electronics computer technology pp 224---228, 2011) for ALU. There is 38.63 % reduction in I/O Power and 46.42 % reduction in leakage power, when we scale down capacitance from 50 to 5 pF on 28 nm technology based Kintex-7 FPGA on 100 GHz device operating frequency. FPGA is a Filed Programmable Gate Array. There is 67.05 % reduction in I/O Power when we scale down ambient temperature from 50 to 10 °C on 100 GHz frequency. There are 5 different climates in koppen climate classification. We are taking 5 different values in order to nearly represent 5 climates. Using high profile Heat Sink and 500 LFM Airflow, there is 75.39 % leakage power reduction from the last optimized result of capacitance scaling and 85.84 % leakage power reduction from the initial power dissipation. On 3rd stage, using HSTL I/O Standard, there is 64.53 % power reduction from the initial power dissipation. There is 41.06, 59.26, 78.75 % power reduction from HSTL_II_DCI_18 to HSTL_I_12 on 100, 10 and 1 GHz. On 4th and final stage, using SSTL I/O Standard, there is 81.79 % power reduction from the initial power dissipation. There is 61.83 % reduction in junction temperature, when we apply 500 LFM airflow and high profile heat sink in compare to 250 LFM airflow and no heat sink. LFM is an acronym for Linear Feet per Minute. LFM is a unit of airflow that help us to control junction temperature of FPGA. Unit of leakage power is Watt (W) and Junction Temperature is degree Celsius (°C).

CTHS Based Energy Efficient Thermal Aware Image ALU Design on FPGA

There is 67.04% dynamic power reduction with LVCMOS12 when we migrate from 90-nm Spartan-3 FPGA to 40-nm Virtex-6 FPGA. There is 81.19%, 92.05% dynamic power reduction when using LVCMOS12 in place of HSTL_II_18 and SSTL2_I_DCI respectively. We achieved 65.56%, 72.59% and 73.41% dynamic power reduction in ALU with LVDCI IO standard in place of LVDCI_DV2, HSTL_I, and LVCMOS12 respectively. There is 68.34% and 52.51% dynamic power reduction in ALU when using LVCMOS12 and LVCMOS15 in place of LVCMOS25. There is 62.45% dynamic power reduction in ALU, when we use HSTL_I in place of SSTL2_I_DCI. Power is directly proportional to frequency. With increase in frequency, there is increase in power consumption irrespective of IO standard. LVCMOS is the only IO standard, which takes less power when we upgrade our design to latest FPGA.

Bishwajeet Pandey

Papers

A Study of Today's A.I. through Chatbots and Rediscovery of Machine Intelligence

Mobile DDR IO Standard Based High Performance Energy Efficient Portable ALU Design on FPGA

Clock gating based energy efficient ALU design and implementation on FPGA

CTHS Based Energy Efficient Thermal Aware Image ALU Design on FPGA

Energy efficient design and implementation of ALU on 40nm FPGA