Bob Lucas

Bio: Bob Lucas is an academic researcher from Information Sciences Institute. The author has contributed to research in topics: Petascale computing & HPC Challenge Benchmark. The author has an hindex of 4, co-authored 5 publications receiving 958 citations. Previous affiliations of Bob Lucas include University of Tennessee & University of Southern California.

The International Exascale Software Project roadmap

Abstract: Over the last 20 years, the open-source community has provided more and more software on which the world’s high-performance computing systems depend for performance and productivity. The community has invested millions of dollars and years of effort to build key components. However, although the investments in these separate software elements have been tremendously valuable, a great deal of productivity has also been lost because of the lack of planning, coordination, and key integration of technologies necessary to make them work together smoothly and efficiently, both within individual petascale systems and between different systems. It seems clear that this completely uncoordinated development model will not provide the software needed to support the unprecedented parallelism required for peta/ exascale computation on millions of cores, or the flexibility required to exploit new hardware models and features, such as transactional memory, speculative execution, and graphics processing units. This report describes the work of the community to prepare for the challenges of exascale computing, ultimately combing their efforts in a coordinated International Exascale Software Project.

Introduction to the HPC Challenge Benchmark Suite

Abstract: The HPC Challenge benchmark suite has been released by the DARPA HPCS program to help define the performance boundaries of future Petascale computing systems. HPC Challenge is a suite of tests that examine the performance of HPC architectures using kernels with memory access patterns more challenging than those of the High Performance Linpack (HPL) benchmark used in the Top500 list. Thus, the suite is designed to augment the Top500 list, providing benchmarks that bound the performance of many real applications as a function of memory access characteristics e.g., spatial and temporal locality, and providing a framework for including additional tests. In particular, the suite is composed of several well known computational kernels (STREAM, HPL, matrix multiply--DGEMM, parallel matrix transpose--PTRANS, FFT, RandomAccess, and bandwidth/latency tests--b{sub eff}) that attempt to span high and low spatial and temporal locality space. By design, the HPC Challenge tests are scalable with the size of data sets being a function of the largest HPL matrix for the tested system.

Empirical Performance Tuning of Dense Linear Algebra Software

Abstract: 3 Empirical Performance Tuning of Dense Linear Algebra Software 3 Jack Dongarra and Shirley Moore 3.1 Background and Motivation . . . . . . . . . . . . . . . . . . 4 3.1.1 Importance of Dense Linear Algebra Software . . . . . 4 3.1.2 Dense Linear Algebra Performance Issues . . . . . . . 4 3.1.3 Idea of Empirical Tuning . . . . . . . . . . . . . . . . 5 3.2 ATLAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2.1 Level 3 BLAS Support . . . . . . . . . . . . . . . . . . 6 3.2.2 Level 2 BLAS Support . . . . . . . . . . . . . . . . . . 7 3.2.3 Level 1 BLAS Support . . . . . . . . . . . . . . . . . . 7 3.2.4 LAPACK Support . . . . . . . . . . . . . . . . . . . . 7 3.2.5 Blocking for Higher Levels of Cache . . . . . . . . . . 8 3.2.6 Use of Assembly Code . . . . . . . . . . . . . . . . . . 8 3.2.7 Use of Architectural Defaults . . . . . . . . . . . . . . 8 3.2.8 Search Algorithm . . . . . . . . . . . . . . . . . . . . . 8 3.3 Auto-tuning for Multicore . . . . . . . . . . . . . . . . . . . 9 3.3.1 Tuning outer and inner block sizes . . . . . . . . . . . 9 3.3.2 Validation of pruned search . . . . . . . . . . . . . . . 11 3.4 Auto-tuning for GPUs . . . . . . . . . . . . . . . . . . . . . . 12 3.4.1 GEMM auto-tuner . . . . . . . . . . . . . . . . . . . . 13 3.4.2 Performance Results . . . . . . . . . . . . . . . . . . . 14 3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Computer Architecture, Fifth Edition: A Quantitative Approach

Abstract: The computing world today is in the middle of a revolution: mobile clients and cloud computing have emerged as the dominant paradigms driving programming and hardware innovation today. The Fifth Edition of Computer Architecture focuses on this dramatic shift, exploring the ways in which software and technology in the "cloud" are accessed by cell phones, tablets, laptops, and other mobile computing devices. Each chapter includes two real-world examples, one mobile and one datacenter, to illustrate this revolutionary change. Updated to cover the mobile computing revolutionEmphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms.Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends ("What's Next")Includes three review appendices in the printed text. Additional reference appendices are available online.Includes updated Case Studies and completely new exercises.

Digital Twin: Values, Challenges and Enablers From a Modeling Perspective

Abstract: Digital twin can be defined as a virtual representation of a physical asset enabled through data and simulators for real-time prediction, optimization, monitoring, controlling, and improved decision making. Recent advances in computational pipelines, multiphysics solvers, artificial intelligence, big data cybernetics, data processing and management tools bring the promise of digital twins and their impact on society closer to reality. Digital twinning is now an important and emerging trend in many applications. Also referred to as a computational megamodel, device shadow, mirrored system, avatar or a synchronized virtual prototype, there can be no doubt that a digital twin plays a transformative role not only in how we design and operate cyber-physical intelligent systems, but also in how we advance the modularity of multi-disciplinary systems to tackle fundamental barriers not addressed by the current, evolutionary modeling practices. In this work, we review the recent status of methodologies and techniques related to the construction of digital twins mostly from a modeling perspective. Our aim is to provide a detailed coverage of the current challenges and enabling technologies along with recommendations and reflections for various stakeholders.

Addressing failures in exascale computing

Abstract: We present here a report produced by a workshop on 'Addressing failures in exascale computing' held in Park City, Utah, 4-11 August 2012. The charter of this workshop was to establish a common taxonomy about resilience across all the levels in a computing system, discuss existing knowledge on resilience across the various hardware and software layers of an exascale system, and build on those results, examining potential solutions from both a hardware and software perspective and focusing on a combined approach. The workshop brought together participants with expertise in applications, system software, and hardware; they came from industry, government, and academia, and their interests ranged from theory to implementation. The combination allowed broad and comprehensive discussions and led to this document, which summarizes and builds on those discussions.

Exascale computing and big data

Abstract: Scientific discovery and engineering innovation requires unifying traditionally separated high-performance computing and big data analytics.

Collecting Performance Data with PAPI-C

Abstract: Modern high performance computer systems continue to increase in size and complexity. Tools to measure application performance in these increasingly complex environments must also increase the richness of their measurements to provide insights into the increasingly intricate ways in which software and hardware interact. PAPI (the Performance API) has provided consistent platform and operating system independent access to CPU hardware performance counters for nearly a decade. Recent trends toward massively parallel multi-core systems with often heterogeneous architectures present new challenges for the measurement of hardware performance information, which is now available not only on the CPU core itself, but scattered across the chip and system. We discuss the evolution of PAPI into Component PAPI, or PAPI-C, in which multiple sources of performance data can be measured simultaneously via a common software interface. Several examples of components and component data measurements are discussed. We explore the challenges to hardware performance measurement in existing multi-core architectures. We conclude with an exploration of future directions for the PAPI interface.