Bob Sankman

Bio: Bob Sankman is an academic researcher from Intel. The author has contributed to research in topics: Pin grid array & Die (integrated circuit). The author has an hindex of 6, co-authored 9 publications receiving 118 citations.

Chip package having metal traces not overlapping apertures

Abstract: A semiconductor device package includes multiple build-up layers of metal sandwiching non-conductive layers. The metal layers include apertures, or degassing holes. A manual method and a computer-implemented method for designing the semiconductor device packages includes stepping polygons across a representation of a conductive layer. A signal routing layer that includes signal traces is then superimposed on the conductive layer. Signal traces overlap the polygons creating regions of intersection that can be enlarged. Regions of intersection are removed from the polygons and the remaining polygon area is designated as apertures in the conductive layer. A semiconductor device package and packaged integrated circuit includes apertures in a conductive layer such that the apertures generally form a radial pattern outward from a region on the package. Signal traces also traverse the package generally radially outward such that the traces and the apertures do not overlap. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by trace.

System and method for package socket with embedded power and ground planes

Abstract: A system and method for embedding power and ground planes in a pin grid array (PGA) socket is provided. Integrated circuit pins are inserted into multiple insertion holes of varying dimensions in the power and ground planes. When the cover of the socket is slidably moved, power pins touch the power plane and ground pins touch the ground plane. Decoupling capacitors are also affixed to the substrate. Thus, the power delivery performance of the overall central processing unit (CPU) package is improved. Moreover, the power and ground planes enhance the mechanical strength of the socket which reduces warpage.

Chip package and method

Abstract: A semiconductor device package includes multiple build-up layers of metal sandwiching non-conductive layers. The metal layers include apertures, or degassing holes. A manual method and a computer-implemented method for designing the semiconductor device packages includes stepping polygons across a representation of a conductive layer. A signal routing layer that includes signal traces is then superimposed on the conductive layer. Signal traces overlap the polygons creating regions of intersection that can be enlarged. Regions of intersection are removed from the polygons and the remaining polygon area is designated as apertures in the conductive layer. A semiconductor device package and packaged integrated circuit includes apertures in a conductive layer such that the apertures generally form a radial pattern outward from a region on the package. Signal traces also traverse the package generally radially outward such that the traces and the apertures do not overlap. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by trace.

Protected socket for integrated circuit devices

Abstract: Provided are a method, device and system in which, in one embodiment, a socket for an integrated circuit package includes a standoff adapted to engage and support the package in a first position in which the package contact terminals are disengaged from socket contact terminals. The standoff is adapted to move to a second position in which the package contact terminals are engaged with the socket contact terminals. In another embodiment, male and female alignment members guide package contact terminals into engagement with socket contact terminals.

3D Packaging Architectures and Assembly Process Design

Abstract: In this chapter, the advantages and limitations of 3D architectures are discussed to provide context for why 3D stacking has become a key area of interest for product architects, why it has generated broad industry attention, and why its adoption has been tenous. The primary focus of this chapter is on 3D architectures that use Through Silicon Vias (TSVs), while other System In Package (SIP) architectures that do not rely on TSVs are discussed for completeness. The key elements of a TSV-based 3D architecture are described, followed by a description of the three methods of manufacturing wafers with TSVs (i.e., Via-First, Via-Middle, and Via-Last). An analysis of the different assembly process flows for 3D structures, broadly classified as (a) Wafer-to-Wafer (W2W), (b) Die-to-Wafer (D2W), and (c) Die-to-Die (D2D) assembly processes, is covered. Key design, assembly process, test process, and materials considerations for each of these flows are described. The chapter concludes with a discussion of current and anticipated challenges for 3D architectures.

Adaptive patterning for panelized packaging

Abstract: An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.

Power delivery system for integrated circuits utilizing discrete capacitors

Abstract: Systems for power delivery to an integrated circuit include a decoupling capacitance located in a connector that is formed as a socket, or frame for the IC. The power delivery system delivers power to the IC along various surfaces thereof by way of a plurality of discrete capacitors that are supported by a socket-style connector. The socket-style connector has an insulative body portion that is mounted to a circuit board and has a recess defined thereon that receives the IC therein. A plurality of capacitors are integrated with the body portion and each of the capacitors supplies a desired amount of power to the IC. The capacitors are charged by way of leads on the circuit board that bring power to current to the capacitors and then are discharged as the IC draws power from the socket such that the capacitors form a power reservoir integrated with the socket, thereby eliminating the need for mounting such capacitors on the circuit board near the IC and freeing up space on the circuit board.

Printed circuit board and method of manufacturing the same

Abstract: Provided are a printed circuit board and a method of manufacturing the same, the printed circuit board according to the present invention, the printed circuit board, including: an insulating substrate having a plurality of circuit pattern grooves formed on a surface thereof; and a plurality of circuit patterns formed by burying the circuit pattern grooves, wherein the circuit patterns protrude as much as a predetermined thickness from an upper surface of the insulating substrate.

Power delivery connector for integrated circuits utilizing integrated capacitors

Abstract: A system for delivering power to an integrated circuit includes a decoupling capacitance located in a connector that is formed as a socket, or frame for the IC. The power delivery system takes the form of a power reservoir that is integrated into a connector, thereby eliminating the need for complex and expensive power traces to be formed in or discrete capacitors mounted on a circuit board to which the IC is connected. The system includes a connector that takes the form of a cover member that fits over the IC and which contains a recess that accommodates a portion of the IC therein. The cover member includes at least a pair of spaced-apart capacitor plates that are disposed therewithin. Electricity is supplied to the plates so that they will become charged as a capacitor and the plates are formed with a plurality of terminals that extend into contact with the IC so that the plates may selectively discharge to the IC and thereby provide it with operating and surge currents.

Deep Reinforcement Learning-Based Optimal Decoupling Capacitor Design Method for Silicon Interposer-Based 2.5-D/3-D ICs

Abstract: In this article, we first propose a deep reinforcement learning (RL)-based optimal decoupling capacitor (decap) design method for silicon interposer-based 2.5-D/3-D integrated circuits (ICs). The proposed method provides an optimal decap design that satisfies target impedance with a minimum area. Using deep RL algorithms based on reward feedback mechanisms, an optimal decap design guideline can be derived. For verification, the proposed method was applied to test power distribution networks (PDNs) and self-PDN impedance was compared with full search simulation results. We successfully verified by the full search simulation that the proposed method provides one of the solution sets. Conventional approaches are based on complex analytical models from power integrity (PI) domain expertise. However, the proposed method requires only specifications of the PDN structure and decap, along with a simple reward model, achieving fast and accurate data-driven results. Computing time of the proposed method was a few minutes, significantly reduced than that of the full search simulation, which took more than a month. Furthermore, the proposed deep RL method covered up to $10^{17}$ – $10^{18}$ cases, an approximately $10^{12}$ – $10^{13}$ order increase compared to the previous RL-based methods that did not utilize deep-learning techniques.