Bob Verbruggen

Bio: Bob Verbruggen is an academic researcher from Xilinx. The author has contributed to research in topics: CMOS & Comparator. The author has an hindex of 21, co-authored 55 publications receiving 1415 citations. Previous affiliations of Bob Verbruggen include Katholieke Universiteit Leuven.

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

Abstract: A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna. Very high resilience to out-of-band interference is achieved thanks to a 2.5 V linear LNA and mixer-based RF blocker filter. The 2 mm2, 40 nm digital CMOS receiver achieves +10 dBm out-of-band IIP3 and >; +70 dBm calibrated IIP2 at 3 dB NF. It tolerates 0 dBm blockers at 20 MHz offset with acceptable blocker NF.

A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

Abstract: A 250 MS/s 2x interleaved 11 bit pipelined SAR ADC in 40 nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR with a total of two bits of redundancy. Calibration is leveraged to adjust the uncertain gain of the chosen residue amplifier and various other non-idealities. The ADC achieves a peak SNDR of 62 dB at 10 MS/s, and 56 dB for a Nyquist input at 250 MS/s. The low frequency energy per conversion step ranges from 7 fJ at 10 MS/s to 10 fJ at 250 MS/s.

A 150 MS/s 133 $~\mu$ W 7 bit ADC in 90 nm Digital CMOS

Abstract: In recent years the energy efficiency of A/D converters has been improved significantly. Only 5 years ago [3] an energy efficiency of 1 pJ/conversion step was considered state-of-the-art. Now power efficiencies are reported in f J/conversion step. In this paper two new converter techniques are presented that further improve upon reported energy efficiencies of A/D converters. The first technique implements the quantization with a comparator-based asynchronous binary search (CABS). The second technique implements the SAR control algorithm on the comparators (SAR-CC) that are also used to do the quantization. Both these techniques have been applied in a fully dynamic 7 bit A/D converter that uses a two-step lb coarse and 6b fine architecture [2]. The 1b coarse converter is implemented using the SAR-CC principle, the 6b fine converter is implemented using the CABS principle. The 7 bit prototype implementation in 90 nm digital CMOS on a 1 V supply achieves 6.4ENOB, 40 dB SNDR at 150 MS/s consuming 133 muW giving 10 fJ/conversion step energy efficiency (FOM). A second prototype implementing a stand-alone 6b CABS converter (the sub-A/D converter of the 7 bit converter) achieves 32 dB SNDR at 250 MS/s with 140 muW of power consumption, which results in a FOM of 15 fJ/conversion step.

A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS

Abstract: A 5 bit 175 GS/s ADC using a factor 2 dynamic folding technique is presented The 2X folding lowers the number of comparators from 31 to 16, simplifies encoding and reduces power consumption and area The comparators in this converter are implemented with built-in references and calibration to further reduce power consumption INL and DNL after calibration are smaller than 03 LSB, with an SNDR of 299 dB at low frequencies, and above 275 dB up to the Nyquist frequency The converter consumes 22 mW from a 1 V supply, yielding a FoM of 50 fJ per conversion step and occupies 002 mm2 in a 90 nm 1P9M digital CMOS process

A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS

Abstract: We present a 200 MS/s 2x interleaved 14 bit pipelined SAR ADC in 28nm digital CMOS. The ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration. The ADC achieves a peak SNDR of 70.7 dB at 200 MS/s while consuming 2.3 mW from an 0.9 V supply.

Memristor-Based Analog Computation and Neural Network Classification with a Dot Product Engine.

Abstract: Using memristor crossbar arrays to accelerate computations is a promising approach to efficiently implement algorithms in deep neural networks. Early demonstrations, however, are limited to simulations or small-scale problems primarily due to materials and device challenges that limit the size of the memristor crossbar arrays that can be reliably programmed to stable and analog values, which is the focus of the current work. High-precision analog tuning and control of memristor cells across a 128 × 64 array is demonstrated, and the resulting vector matrix multiplication (VMM) computing precision is evaluated. Single-layer neural network inference is performed in these arrays, and the performance compared to a digital approach is assessed. Memristor computing system used here reaches a VMM accuracy equivalent of 6 bits, and an 89.9% recognition accuracy is achieved for the 10k MNIST handwritten digit test set. Forecasts show that with integrated (on chip) and scaled memristors, a computational efficiency greater than 100 trillion operations per second per Watt is possible.

Attojoule Optoelectronics for Low-Energy Information Processing and Communications

Abstract: Optics offers unique opportunities for reducing energy in information processing and communications while simultaneously resolving the problem of interconnect bandwidth density inside machines. Such energy dissipation overall is now at environmentally significant levels; the source of that dissipation is progressively shifting from logic operations to interconnect energies. Without the prospect of substantial reduction in energy per bit communicated, we cannot continue the exponential growth of our use of information. The physics of optics and optoelectronics fundamentally addresses both interconnect energy and bandwidth density, and optics may be the only scalable solution to such problems. Here we summarize the corresponding background, status, opportunities, and research directions for optoelectronic technology and novel optics, including subfemtojoule devices in waveguide and novel two-dimensional (2-D) array optical systems. We compare different approaches to low-energy optoelectronic output devices and their scaling, including lasers, modulators and LEDs, optical confinement approaches (such as resonators) to enhance effects, and the benefits of different material choices, including 2-D materials and other quantum-confined structures. With such optoelectronic energy reductions, and the elimination of line charging dissipation by the use optical connections, the next major interconnect dissipations are in the electronic circuits for receiver amplifiers, timing recovery, and multiplexing. We show we can address these through the integration of photodetectors to reduce or eliminate receiver circuit energies, free-space optics to eliminate the need for timing and multiplexing circuits (while also solving bandwidth density problems), and using optics generally to save power by running large synchronous systems. One target concept is interconnects from ∼1 cm to ∼10 m that have the same energy (∼10 fJ/bit) and simplicity as local electrical wires on chip.

A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$ W at 1 MS/s

Abstract: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115×225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

Abstract: A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

Attojoule Optoelectronics for Low-Energy Information Processing and Communications: a Tutorial Review

Abstract: Optics offers unique opportunities for reducing energy in information processing and communications while resolving the problem of interconnect bandwidth density inside machines. Such energy dissipation overall is now at environmentally significant levels; the source of that dissipation is progressively shifting from logic operations to interconnect energies. Without the prospect of substantial reduction in energy per bit communicated, we cannot continue the exponential growth of our use of information. The physics of optics and optoelectronics fundamentally addresses both interconnect energy and bandwidth density, and optics may be the only scalable solution to such problems. Here we summarize the corresponding background, status, opportunities, and research directions for optoelectronic technology and novel optics, including sub-femtojoule devices in waveguide and novel 2D array optical systems. We compare different approaches to low-energy optoelectronic output devices and their scaling, including lasers, modulators and LEDs, optical confinement approaches (such as resonators) to enhance effects, and the benefits of different material choices, including 2D materials and other quantum-confined structures. Beyond the elimination of line charging by the use optical connections, the next major interconnect dissipations are in the electronic circuits for receiver amplifiers, timing recovery and multiplexing. We can address these through the integration of photodetectors to reduce or eliminate receiver circuit energies, free-space optics to eliminate the need for timing and multiplexing circuits (while solving bandwidth density problems), and using optics generally to save power by running large synchronous systems. One target concept is interconnects from ~ 1 cm to ~ 10 m that have the same energy (~ 10fJ/bit) and simplicity as local electrical wires on chip.