Boon Teik Chan

Bio: Boon Teik Chan is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Plasma etching & Layer (electronics). The author has an hindex of 13, co-authored 65 publications receiving 469 citations. Previous affiliations of Boon Teik Chan include Tokyo Electron.

A Thermally Stable and High-Performance 90-nm ${\rm Al}_{2}{\rm O}_{3}\backslash{\rm Cu}$ -Based 1T1R CBRAM Cell

Abstract: In this paper, we optimize the stack of a 90-nm CMOS-friendly W\Al2O3\Cu conductive-bridging random access memory cell integrated in the one-transistor/one-resistor configuration. We show that the excellent Cu buffering properties of a TiW layer inserted at the Al2O3\Cu interface make it possible, on one hand, to ensure cell integrity after back-end-of-line processing at 400 °C and, on the other, to obtain excellent memory performances. After optimization of the Al2O3 layer thickness, the cell exhibits highly controlled set and reset operations, a large memory window, fast pulse programming (0 ns) at low voltage (<;3 V), and low-current (10 μA), and multilevel operation. Finally, 106 cycles of write endurance lifetime with up to a three-decade memory window is demonstrated, and state stability is assessed up to 125 °C.

Area-Selective Atomic Layer Deposition of TiN, TiO2, and HfO2 on Silicon Nitride with inhibition on Amorphous Carbon

Abstract: The demand for transistors and memory devices with smaller feature sizes and increasingly complex architectures furthers the need for advanced thin film patterning techniques. A prepatterned, sacrificial layer can be used as a template for bottom-up fill of new materials which would otherwise be difficult to pattern using traditional top-down lithographic methods. This work investigates initial growth of TiN, TiO2, and HfO2 thin films during thermal atomic layer deposition (ALD) onto a high density, amorphous carbon (aC) sacrificial layer. ALD of TiN by TiCl4/NH3 at 390 °C, TiO2 by Ti(OCH3)4/H2O at 250 °C, and HfO2 by HfCl4/H2O at 300 °C on as-deposited aC films resulted in uninhibited, continuous thin film growth. We find that carbon surface reduction and passivation using a H2 plasma resulted in delayed film coalescence for TiN, TiO2, and HfO2 on the aC. After 200 TiN cycles on H2 plasma-treated aC, Rutherford backscattering spectrometry shows Ti levels below the detection limit (8 × 1013 at/cm2), where...

First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers

Abstract: We report the first monolithic integration of 3D Complementary Field Effect Transistor (CFET) on 300mm wafers using imec's N14 platform. A monolithic CFET process is cost effective compared to a sequential CFET process. The small N/P separation in a monolithic CFET results in lower parasitics and higher performance gains. In this paper, using a CFET fabrication process flow, we demonstrate functional PMOS FinFET bottom devices and NMOS nanosheet FET top devices. Process development of all the critical modules to enable these devices are presented. Monolithic CFET integration scheme could enable the ultimate device footprint scaling required in future technology nodes.

Defect mitigation and root cause studies in 14 nm half-pitch chemo-epitaxy directed self-assembly LiNe flow

Abstract: High-defect density in thermodynamics driven directed self-assembly (DSA) flows has been a major cause of concern for a while and several questions have been raised about the relevance of DSA in high-volume manufacturing. The major questions raised in this regard are: (1) What is the intrinsic level of DSA-induced defects? (2) Can we isolate the DSA-induced defects from the other processes-induced defects? (3) How much do the DSA materials contribute to the final defectivity and can this be controlled? (4) How can we understand the root causes of the DSA-induced defects and their kinetics of annihilation? (5) Can we have block copolymer anneal durations that are compatible with standard CMOS fabrication techniques (in the range of minutes) with low-defect levels? We address these important questions and identify the issues and the level of control needed to achieve a stable DSA defect performance.

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells

Abstract: We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower I OFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (W NW ≤25nm, H NW ∼22nm), with increased doping enabling ION improvement without I OFF penalty for W NW ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. V T mismatch performance shows higher A VT with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (d NW ≥20–30nm), integrated on the same 300mm Si platform as lateral devices. Low I OFF , I G , and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n/n or p/p) to reduce SRAM area per bit by 39%.

Resistive switching memories based on metal oxides: mechanisms, reliability and scaling

Abstract: With the explosive growth of digital data in the era of the Internet of Things (IoT), fast and scalable memory technologies are being researched for data storage and data-driven computation. Among the emerging memories, resistive switching memory (RRAM) raises strong interest due to its high speed, high density as a result of its simple two-terminal structure, and low cost of fabrication. The scaling projection of RRAM, however, requires a detailed understanding of switching mechanisms and there are potential reliability concerns regarding small device sizes. This work provides an overview of the current understanding of bipolar-switching RRAM operation, reliability and scaling. After reviewing the phenomenological and microscopic descriptions of the switching processes, the stability of the low- and high-resistance states will be discussed in terms of conductance fluctuations and evolution in 1D filaments containing only a few atoms. The scaling potential of RRAM will finally be addressed by reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM a strong competitor among future high-density memory solutions.

Recommended Methods to Study Resistive Switching Devices

Abstract: Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, with electronic nonvolatile memories being those that have received the most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. This manuscript describes the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Electronic synapses made of layered two-dimensional materials

Abstract: Neuromorphic computing systems, which use electronic synapses and neurons, could overcome the energy and throughput limitations of today’s computing architectures. However, electronic devices that can accurately emulate the short- and long-term plasticity learning rules of biological synapses remain limited. Here, we show that multilayer hexagonal boron nitride (h-BN) can be used as a resistive switching medium to fabricate high-performance electronic synapses. The devices can operate in a volatile or non-volatile regime, enabling the emulation of a range of synaptic-like behaviour, including both short- and long-term plasticity. The behaviour results from a resistive switching mechanism in the h-BN stack, based on the generation of boron vacancies that can be filled by metallic ions from the adjacent electrodes. The power consumption in standby and per transition can reach as low as 0.1 fW and 600 pW, respectively, and with switching times reaching less than 10 ns, demonstrating their potential for use in energy-efficient brain-like computing. Vertically structured electronic synapses, which exhibit both short- and long-term plasticity, can be created using layered two-dimensional hexagonal boron nitride.

A comprehensive review on emerging artificial neuromorphic devices

Abstract: The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.