Boyd Fowler

Bio: Boyd Fowler is an academic researcher from Fairchild Semiconductor International, Inc.. The author has contributed to research in topics: Image sensor & Pixel. The author has an hindex of 21, co-authored 53 publications receiving 2762 citations. Previous affiliations of Boyd Fowler include Agilent Technologies & Stanford University.

Analysis of temporal noise in CMOS photodiode active pixel sensor

Abstract: Temporal noise sets the fundamental limit on image sensor performance, especially under low illumination and in video applications. In a CCD image sensor, temporal noise is primarily due to the photodetector shot noise and the output amplifier thermal and 1/f noise. CMOS image sensors suffer from higher noise than CCDs due to the additional pixel and column amplifier transistor thermal and 1/f noise. Noise analysis is further complicated by the time-varying circuit models, the fact that the reset transistor operates in subthreshold during reset, and the nonlinearity of the charge to voltage conversion, which is becoming more pronounced as CMOS technology scales. The paper presents a detailed and rigorous analysis of temporal noise due to thermal and shot noise sources in CMOS active pixel sensor (APS) that takes into consideration these complicating factors. Performing time-domain analysis, instead of the more traditional frequency-domain analysis, we find that the reset noise power due to thermal noise is at most half of its commonly quoted kT/C value. This result is corroborated by several published experimental data including data presented in this paper. The lower reset noise, however, comes at the expense of image lag. We find that alternative reset methods such as overdriving the reset transistor gate or using a pMOS transistor can alleviate lag, but at the expense of doubling the reset noise power. We propose a new reset method that alleviates lag without increasing reset noise.

A 640/spl times/512 CMOS image sensor with ultra wide dynamic range floating-point pixel-level ADC

Abstract: Analysis results demonstrate that multiple sampling can achieve consistently higher signal-to-noise ratio at equal or higher dynamic range than using other image sensor dynamic range enhancement schemes such as well capacity adjusting. Implementing multiple sampling, however, requires much higher readout speeds than can be achieved using typical CMOS active pixel sensor (APS). This paper demonstrates, using a 640/spl times/512 CMOS image sensor with 8-b bit-serial Nyquist rate analog-to-digital converter (ADC) per 4 pixels, that pixel-level ADC enables a highly flexible and efficient implementation of multiple sampling to enhance dynamic range. Since pixel values are available to the ADC's at all times, the number and timing of the samples as well as the number of bits obtained from each sample can be freely selected and read out at fast SRAM speeds. By sampling at exponentially increasing exposure times, pixel values with binary floating-point resolution can be obtained. The 640/spl times/512 sensor is implemented in 0.35-/spl mu/m CMOS technology and achieves 10.5/spl times/10.5 /spl mu/m pixel size at 29% fill factor. Characterization techniques and measured quantum efficiency, sensitivity, ADC transfer curve, and fixed pattern noise are presented. A scene with measured dynamic range exceeding 10000:1 is sampled nine times to obtain an image with dynamic range of 65536:1. Limits on achievable dynamic range using multiple sampling are presented.

Cmos image sensor with pixel level a/d conversion

Abstract: An image sensor formed using a CMOS process is described herein which includes a pixel array core of phototransistors whose conductivities are related to the magnitude of light impinging upon the phototransistors. The analog signals generated by the phototransistors are converted to a serial bit stream by an A/D converter connected at the output of each phototransistor and formed in the immediate area of each phototransistor within the array core. Thus, a separate digital stream for each pixel element is output from the array core, and parasitic effects and distortion are minimized. In one embodiment, a filter circuit is connected to an output of the array core for converting the individual digital streams from each pixel element to multi-bit values corresponding to the intensity of light impinging on the phototransistor.

Serial analog-to-digital converter using successive comparisons

Abstract: A method for simultaneously performing bit serial analog to digital conversion (ADC) for a potentially very large number of signals is described. The method is ideally suited for performing on chip ADC in area image sensors. In one embodiment, to achieve N-bit precision, the method employs a one-bit comparator per channel (or set of multiplexed channels) and an N-bit DAC. To achieve N bits of precision, 2 N -1 comparisons are sequentially performed. Each comparison is performed by first setting the DAC output to the desired value and then simultaneously comparing each of the pixel values to that value. If a pixel value is greater than the DAC output value, its comparator outputs a one, otherwise it outputs a zero. By appropriately choosing the sequence of comparison values, the pixel values are sequentially generated. In another embodiment, the DAC is omitted and a continuous ramp signal is generated for comparison with the analog input.

A CMOS area image sensor with pixel-level A/D conversion

Abstract: Charge-coupled devices (CCD) are at present the most widely used technology for implementing area image sensors. However, they suffer from low yields, consume too much power, and are plagued with SNR limitations due to the shifting and detection of analog charge packets, and the fact that data is communicated off chip in analog form. This paper describes an area image sensor that can potentially circumvent the limitations of CCDs and their alternatives. It uses a standard CMOS process and can therefore be manufactured with high yield. Digital circuitry for control and signal processing can be integrated with the sensor. Moreover, CMOS technology advances such as scaling and extra layers of metal can be used to improve pixel density and sensor performance. The analog image data is immediately converted to digital at each pixel using a one-bit sigma-delta modulator. The use of sigma-delta modulation allows the data-conversion circuitry to be simple and insensitive to process variations. A global shutter provides variable light input attenuation to achieve wide dynamic range. Data is communicated off chip in a digital form, eliminating the SNR degradation of analog data communication. To demonstrate the viability of the approach, an area image sensor chip is fabricated in a 1.2 /spl mu/m CMOS technology. The device consists of an array of 64x64 pixel blocks, a clock driver, a 6:64 row address decoder, 64 latched sense amplifiers, and 16 4:1 column multiplexers. The chip also contains data compression circuitry. >

Fast bilateral filtering for the display of high-dynamic-range images

Abstract: We present a new technique for the display of high-dynamic-range images, which reduces the contrast while preserving detail. It is based on a two-scale decomposition of the image into a base layer, encoding large-scale variations, and a detail layer. Only the base layer has its contrast reduced, thereby preserving detail. The base layer is obtained using an edge-preserving filter called the bilateral filter. This is a non-linear filter, where the weight of each pixel is computed using a Gaussian in the spatial domain multiplied by an influence function in the intensity domain that decreases the weight of pixels with large intensity differences. We express bilateral filtering in the framework of robust statistics and show how it relates to anisotropic diffusion. We then accelerate bilateral filtering by using a piecewise-linear approximation in the intensity domain and appropriate subsampling. This results in a speed-up of two orders of magnitude. The method is fast and requires no parameter setting.

Image Alignment and Stitching: A Tutorial

Abstract: This tutorial reviews image alignment and image stitching algorithms. Image alignment algorithms can discover the correspondence relationships among images with varying degrees of overlap. They are ideally suited for applications such as video stabilization, summarization, and the creation of panoramic mosaics. Image stitching algorithms take the alignment estimates produced by such registration algorithms and blend the images in a seamless manner, taking care to deal with potential problems such as blurring or ghosting caused by parallax and scene movement as well as varying image exposures. This tutorial reviews the basic motion models underlying alignment and stitching algorithms, describes effective direct (pixel-based) and feature-based alignment algorithms, and describes blending algorithms used to produce seamless mosaics. It ends with a discussion of open research problems in the area.

CMOS image sensors: electronic camera-on-a-chip

Abstract: CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed.

Methods and apparatus for measuring analytes using large scale fet arrays

Abstract: An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Determining Image Origin and Integrity Using Sensor Noise

Abstract: In this paper, we provide a unified framework for identifying the source digital camera from its images and for revealing digitally altered images using photo-response nonuniformity noise (PRNU), which is a unique stochastic fingerprint of imaging sensors. The PRNU is obtained using a maximum-likelihood estimator derived from a simplified model of the sensor output. Both digital forensics tasks are then achieved by detecting the presence of sensor PRNU in specific regions of the image under investigation. The detection is formulated as a hypothesis testing problem. The statistical distribution of the optimal test statistics is obtained using a predictor of the test statistics on small image blocks. The predictor enables more accurate and meaningful estimation of probabilities of false rejection of a correct camera and missed detection of a tampered region. We also include a benchmark implementation of this framework and detailed experimental validation. The robustness of the proposed forensic methods is tested on common image processing, such as JPEG compression, gamma correction, resizing, and denoising.