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Brian D. Hoskins

Researcher at National Institute of Standards and Technology

Publications -  53
Citations -  4636

Brian D. Hoskins is an academic researcher from National Institute of Standards and Technology. The author has contributed to research in topics: Memristor & Neuromorphic engineering. The author has an hindex of 19, co-authored 49 publications receiving 3658 citations. Previous affiliations of Brian D. Hoskins include University of California & University of California, Santa Barbara.

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Training and operation of an integrated neuromorphic network based on metal-oxide memristors

TL;DR: The experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification).
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High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm

TL;DR: Using memristive properties common for titanium dioxide thin film devices, this article designed a simple write algorithm to tune device conductance at a specific bias point to 1% relative accuracy within its dynamic range even in the presence of large variations in switching behavior.
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High-Precision Tuning of State for Memristive Devices by Adaptable Variation-Tolerant Algorithm

TL;DR: A simple write algorithm is designed to tune device conductance at a specific bias point to 1% relative accuracy (which is roughly equivalent to seven-bit precision) within its dynamic range even in the presence of large variations in switching behavior.
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3-D Memristor Crossbars for Analog and Neuromorphic Computing Applications

TL;DR: The integrated crosspoint memristors are optimized for analog computing applications allowing successful forming and switching of all 200 devices in the demonstrated crossbar circuit, and, most importantly, precise tuning of the devices' conductance values within the dynamic range of operation.
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Resistive switching and its suppression in Pt/Nb:SrTiO3 junctions

TL;DR: An unintentional interface layer is identified as the origin of resistive switching in Pt/Nb:SrTiO3 junctions and it is shown that appropriate interface processing can eliminate this contribution.