Brian J. Greene

Bio: Brian J. Greene is an academic researcher from IBM. The author has contributed to research in topics: Field-effect transistor & Gate oxide. The author has an hindex of 19, co-authored 86 publications receiving 1393 citations. Previous affiliations of Brian J. Greene include GlobalFoundries & Chartered Semiconductor Manufacturing.

Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors

Abstract: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

High performance 14nm SOI FinFET CMOS technology with 0.0174µm 2 embedded DRAM and 15 levels of Cu metallization

Abstract: We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um2) memory solution for industry leading ‘scale-out’ processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ∼0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.

Structure and method for improved stress and yield in pFETS with embedded SiGe source/drain regions

Abstract: The present invention provides a technique for forming a CMOS structure including at least one pFET that has a stressed channel which avoids the problems mentioned in the prior art. Specifically, the present invention provides a method for avoiding formation of deep canyons at the interface between the active area and the trench isolation region, without requiring a trench isolation pulldown, thereby eliminating the problems of silicide to source/drain shorts and contact issues. At the same time, the method of the present invention provides a structure that allows for a facet to form at the spacer edge, retaining the Miller capacitance benefit that such a structure provides. The inventive structure also results in higher uniaxial stress in the MOSFET channel compared to one which allows for a facet to grow at the trench isolation edge.

Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage

Abstract: A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper

Abstract: This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 µm2. V min operation down to 0.6 V in a 16Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by hig-hk/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress liner (DSL). Gate lengths down to 25 nm have been demonstrated enabling performance without the power penalty from gate capacitance. AC drive currents of 1.55 mA/um and 1.22 mA/um have been achieved at an off-state of 100 nA/µm and V DD of 1 V for NFET and PFET, respectively. For the first time, we have also demonstrated that SOI maintains performance benefit over bulk silicon in high-k/metal gate and 32 nm ground rules.

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Design Of Analog Cmos Integrated Circuits

Abstract: Thank you for downloading design of analog cmos integrated circuits. Maybe you have knowledge that, people have look hundreds times for their chosen books like this design of analog cmos integrated circuits, but end up in malicious downloads. Rather than enjoying a good book with a cup of coffee in the afternoon, instead they juggled with some harmful virus inside their computer. design of analog cmos integrated circuits is available in our book collection an online access to it is set as public so you can download it instantly. Our digital library spans in multiple countries, allowing you to get the most less latency time to download any of our books like this one. Kindly say, the design of analog cmos integrated circuits is universally compatible with any devices to read.

Substrate Processing Apparatus

Abstract: Process gas discharged from a bypass pipe to a gas exhaust system can be prevented from diffusing back to the inside of a process chamber without having to install a dedicated vacuum pump at the downstream side of the bypass pipe. The substrate processing apparatus includes a process chamber accommodating a substrate, a gas supply system supplying process gas from a process gas source to the process chamber for processing the substrate, a gas exhaust system configured to exhaust the process chamber, two or more vacuum pumps installed in series at the gas exhaust system, and a bypass pipe connected between the gas supply system and the gas exhaust system. The most upstream one of the vacuum pumps is a mechanical booster pump, and the bypass pipe is connected between the mechanical booster pump and the rest vacuum pumps located at a downstream side of the mechanical booster pump.

Contact Structure of Semiconductor Device

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.

Strain: A Solution for Higher Carrier Mobility in Nanoscale MOSFETs

Abstract: Metal-oxide-semiconductor field-effect transistors (MOSFETs) have shown impressive performance improvements over the past 10 years by incorporating strained silicon (Si) technology. This review gives an overview of the impact of strain on carrier mobility in Si n- and pMOSFETs by considering strain-induced band splitting, band warping and consequent carrier repopulation, and altered conductivity effective mass and scattering rate. Different surface orientations, channel directions, and gate electric fields are included for a fully theoretical understanding. The results are used to predict strain-enhanced silicon-on-insulator (SOI) and multigate device performance, mainly focusing on potential 22-nm and beyond device options such as double-gate and trigate fin field-effect transistor (FinFET) structures. Insights into strain-enhanced potential future channel materials (SiGe, Ge, and GaAs) are also summarized. Finally, recent technology nodes with strain engineering are reviewed, and the future developing t...