Brice Achkir

Abstract: Through-silicon-via (TSV) enables vertical connectivity between stacked chips or interposer and is a key technology for 3-D integrated circuits (ICs) While arrays of TSVs are needed in 3-D IC, there only exists a frequency-dependent resistance, inductance, conductance and capacitance circuit model for a pair of TSVs with coupling between them In this paper, we develop a simple yet accurate circuit model for a multiport TSV network (eg, coupled TSV array) by decomposing the network into a number of TSV pairs and then applying circuit models for each of them We call the new model a pair-based model for the multiport TSV network It is first verified against a commercial electromagnetic solver for up to 20 GHz and subsequently employed for a variety of examples for signal and power integrity analysis

Abstract: The transfer functions relating supply voltage fluctuations to jitter are analytically derived in closed form expressions for a single-ended buffer. The analytic transfer functions are derived from a linear differential equation obtained from asymptotic linear inverter I-V curves. The transfer functions are validated by comparison with HSPICE simulations. The estimated jitter is compared with the simulated jitter using eye diagrams with single-frequency and multitone supply voltage fluctuations.

Abstract: In this paper, the transfer function of a supply voltage fluctuation to jitter is analytically solved for a single ended buffer in closed-form expressions. The expressions for the jitter transfer function is validated by comparison with HSPICE simulation, and applied to an example for statistical jitter estimation.

Abstract: A scalable signal processing test device and related signal processing techniques are provided herein for processing signals at a signal processing module of the scalable signal processing test device. Source electrical signals are processed to generate test electrical signals that model electrical signals produced by an optical module from received optical signals in accordance with a high speed optical standard for optical transmission. The test electrical signals are transmitted over transmit links to a host device that is configured to receive the test electrical signals in a format that would normally be produced by an optical module in accordance with the high speed optical standard. The test electrical signals are received after they have been looped back from the host device over receive links from the host device. The host device is a device that is configured to output the test electrical signals in a format suitable for processing by an optical module in accordance with the high speed optical standard. The test electrical signals received from the host device are analyzed in order to determine whether the host device outputs the one or more sets of test electrical signals in compliance with the high speed optical standard.

Abstract: A methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented. The proposed model is based on inductance extraction from first principle formulation of a cavity formed by parallel metal planes. Circuit reduction is used to practically realize the model for a production level, complex, multilayer PCBs. The lumped element model is compatible with SPICE-type simulators. The resulting model has a relatively simple circuit topology. The model is corroborated with microprobing measurements up to a few gigahertz. The model can be used for a wide range of geometry variations in a power integrity analysis, including complex power/ground stack up, various numbers of decoupling capacitors with arbitrary locations, numerous IC power pins and IC power/ground return via layouts, as well as hundreds of ground return vias.

Abstract: The present disclosure encompasses three-dimensional articles comprising flexible-composite materials and methods of manufacturing said three-dimensional articles. More particularly, the present system relates to methods for manufacturing seamless three-dimensional-shaped articles usable for such finished products as airbags/inflatable structures, bags, shoes, and similar three-dimensional products. A preferred manufacturing process combines composite molding methods with specific precursor materials to form fiber-reinforced continuous shaped articles that are flexible and collapsible.

Abstract: A distributed virtual chassis comprises scaled-out fabric coupler (SFC) boxes. Each SFC box has fabric ports and a cell-based switch fabric for switching cells associated with a packet among the SFC fabric ports of that SFC box. Distributed line cards (DLCs) include switching DLCs and an appliance DLC (A-DLC). Each switching DLC has network ports. Each switching DLC and A-DLC has DLC fabric ports. Each switching DLC and A-DLC is connected to each of the SFC boxes. The A-DLC provides an upper layer service for packets arriving on the network ports of the switching DLCs. To forward a packet to the A-DLC, a switching DLC divides the packet into cells and distributes the cells among the SFC boxes. The SFC boxes forward the cells to the A-DLC, and the A-DLC reassembles the packet from the cells and provides the upper layer service to the packet.

Abstract: Copper foil in printed circuit board (PCB) transmission lines/interconnects is roughened to promote adhesion to dielectric substrates. It is important to characterize PCB substrate dielectrics and correctly separate dielectric and conductor losses, especially as data rates in high-speed digital designs increase. Herein, a differential method is proposed for separating conductor and dielectric losses in PCBs with rough conductors. This approach requires at least three transmission lines with identical, or at least as close as technologically possible, basic geometry parameters of signal trace, distance-to-ground planes, and dielectric properties, while the average peak-to-valley amplitude of surface roughness of the conductor would be different. The peak-to-valley amplitude of conductor roughness is determined from scanning electron microscopy images.