There has been a surge of interest in Non-Volatile Memory (NVM) in recent years. With many advantages, such as density and power consumption, NVM is carving out a place in the memory hierarchy and may eventually change our view of computer architecture. Many NVMs have emerged, such as Magnetoresistive random access memory (MRAM), Phase Change random access memory (PCM), Resistive random access memory (ReRAM), and Ferroelectric random access memory (FeRAM), each with its own peculiar properties and specific challenges. The scientific community has carried out a substantial amount of work on integrating those technologies in the memory hierarchy. As many companies are announcing the imminent mass production of NVMs, we think that it is time to have a step back and discuss the body of literature related to NVM integration. This article surveys state-of-the-art work on integrating NVM into the memory hierarchy. Specially, we introduce the four types of NVM, namely, MRAM, PCM, ReRAM, and FeRAM, and investigate different ways of integrating them into the memory hierarchy from the horizontal or vertical perspectives. Here, horizontal integration means that the new memory is placed at the same level as an existing one, while vertical integration means that the new memory is interleaved between two existing levels. In addition, we describe challenges and opportunities with each NVM technique.

Emerging NVM: A Survey on Architectural Integration and Research Challenges

Magnetoresistive random access memory (MRAM) is regarded as a reliable persistent memory technology because of its long data retention and robust endurance. Initial MRAM products utilized toggle mode writing of a balanced synthetic antiferromagnet (SAF) free layer to overcome problems with half-selected bits that challenged traditional Stoner–Wohlfarth switching. With the development of spin transfer torque (STT) switching in perpendicular magnetic tunnel junctions, the capability for scaling MRAM products increased markedly, enabling a 1-Gb device in 2019. Ongoing research will allow scaling to even higher capacities. Compared to traditional memories, STT-MRAM can save power, improve performance, and enhance system data integrity, which supports the growing computing demands for everything from data centers to Internet of Things (IoT) devices. This article provides a review of the technology that enabled present toggle and STT-MRAM products, future STT-MRAM products, and new MRAM technologies beyond STT.

Magnetoresistive Random Access Memory: Present and Future

Water plays a crucial role in the agricultural field for food production and raising livestock. Given the current trends in world population growth, the urgent food demand that must be answered by agriculture highly depends on our ability to efficiently exploit the available water resources. Among critical issues, there is water management. Recently, innovative technologies have improved water management and monitoring in agriculture. Internet of Things, Wireless Sensor Networks and Cloud Computing, have been used in diverse contexts in agriculture. By focusing on the water management challenge in general, existing approaches are aiming at optimizing water usage, and improving the quality and quantity of agricultural crops, while minimizing the need for direct human intervention. This is achieved by smoothing the water monitoring process, by applying the right automation level, and allowing farmers getting connected anywhere and anytime to their farms. There are plenty of challenges in agriculture involving water: water pollution monitoring, water reuse, monitoring water pipeline distribution network for irrigation, drinking water for livestock, etc. Several studies have been devoted to these questions in the recent decade. Therefore, this paper presents a survey on recent works dealing with water management and monitoring in agriculture, supported by advanced technologies. It also discusses some open challenges based on which relevant research directions can be drawn in the future, regarding the use of modern smart concepts and tools for water management and monitoring in the agriculture domain.

https://hal-lirmm.ccsd.cnrs.fr/lirmm-02506701/document

Water Management in Agriculture: A Survey on Current Challenges and Technological Solutions

As existing silicon-based memory technologies are reaching their fundamental limit, emerging memory alternatives, such as resistive random‐access memories (RRAMs), magnetic random‐access memories, and ferroelectric random‐access memories, are intensively investigated with the aim of improving capacity, write/read speed, efficiency, and implementing unconventional computing for data-centric applications. Recent studies have exploited the nature of 2-dimensional layered materials (2DLMs) to integrate highly disparate materials with unique physical and chemical properties without the constraint of lattice matching and have demonstrated novel memory devices (such as resistive and magnetic) with unprecedented characteristics or unique functionalities desired in emerging memory technologies. This article primarily provides an overview of the progress made, advantages, and challenges toward practical application of 2DLM-based memory units. In this regard, novel electronic properties of these 2DLMs allow designing not only the memory unit but also selectors and CMOS components essential for RRAM technology. Here, we also experimentally demonstrate a proof-of-concept heterostructure consisting of 2DLMs that fulfill the function of a memory unit (using MoTe2) and selector (using WSe2) with desired characteristics for RRAM integration. This demonstration underscores the potential of 2DLMs and their heterostructure toward the realization of future memory technologies.

Memory applications from 2D materials

A variety of systems with possibly embedded computing power, such as small portable robots, hand-held computers, and automated vehicles, have power supply constraints. Their batteries generally last only for a few hours before being replaced or recharged. It is important that all design efforts are made to conserve power in those systems. Energy consumption in a system can be reduced using a number of techniques, such as low-power electronics, architecture-level power reduction, compiler techniques, to name just a few. However, energy conservation at the application software-level has not yet been explored. In this paper, we show the impact of various software implementation techniques on energy saving. Based on the observation that different instructions of a processor cost different amount of energy, we propose three energy saving strategies, namely (i) assigning live variables to registers, (ii) avoiding repetitive address computations, and (iii) minimizing memory accesses. We also study how a variety of algorithm design and implementation techniques affect energy consumption. In particular, we focus on the following aspects: (i) recursive versus iterative (with stacks and without stacks), (ii) different representations of the same algorithm, (iii) different algorithms - with identical asymptotic complexity - for the same problem, and (iv) different input representations. We demonstrate the energy saving capabilities of these approaches by studying a variety of applications related to power-conscious systems, such as sorting, pattern matching, matrix operations, depth-first search, and dynamic programming. From our experimental results, we conclude that by suitably choosing an algorithm for a problem and applying the energy saving techniques, energy savings in excess of 60% can be achieved.

Software implementation strategies for power-conscious systems.

It has become increasingly challenging to respect Moore's well-known law in recent years. Energy efficiency and manufacturing constraints are among the main challenges to current integrated circuits today. The energy efficiency issue is mainly due to the high leakage current from the CMOS transistors that are used to build almost all logic devices. As a result, performance is limited to a few gigahertz due to high power dissipation. A significant proportion of total power is spent on memory systems due to the increasing trend of embedding volatile memory into systems-on-chip devices. New non-volatile memory technologies are one possible way to solve the energy efficiency issue. Among these technologies, magnetic memory is a promising candidate to replace current memories since it combines non-volatility, high density, low latency and low leakage. This paper describes an approach to obtain large, fine-grained exploration of how magnetic memory can be included in the memory hierarchy of processor-based systems by analyzing both performance and energy consumption.

/pdf/exploring-mram-technologies-for-energy-efficient-systems-on-55ka8jecht.pdf

Exploring MRAM Technologies for Energy Efficient Systems-On-Chip

Most die area of today's systems-on-chips is occupied by memories. Hence, a significant proportion of total power is spent on memory systems. Moreover, since processing elements have to be fed with instructions and data from memories, memory plays a key role for system's performance. As a result, memories are a critical part of future embedded systems. Continuing CMOS scaling leads to manufacturing constraints and power consumption issues for the current three main memory technologies, i.e. SRAM, DRAM and FLASH, which compromises further evolution in upcoming technology node. To face these challenges, new non-volatile memory technologies emerged in recent years. Among these technologies, magnetic RAM (MRAM) is a promising candidate to replace existing memories since it combines non-volatility, high scalability, high density, low latency, and low leakage. This paper describes an evaluation flow to explore next generation of the memory hierarchy of processor-based systems using new non-volatile memory technologies.

https://hal-lirmm.ccsd.cnrs.fr/lirmm-01253337/document

Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture

Today's memory systems mainly integrate SRAM, DRAM and FLASH technologies. SRAM and DRAM are generally used for cache and working memory, while FLASH memory is used for non-volatile storage at low speed. But all are facing to manufacturing constraints in the most advanced node, which compromises further evolution. Besides, with the increasing size of the memory system, a significant portion of the total system power is spent into memories. Magnetic RAM (MRAM) technology is a very attractive alternative offering simultaneously reasonable performance and power consumption efficiency, high density and non-volatility. While MRAM is always under severe investigation to improve manufacturing process, the state of the art shows that this memory technology can be accessed in less than 5ns with a read/write dynamic energy not so far to SRAM dynamic energy. Besides, non-volatility of MRAM can be used for optimizing leakage current thanks to instant on/off policies. This paper demonstrates how current characteristics of MRAM can be used into memory hierarchy of multiprocessor chips (CMPs). The goal is to highlight the interest to use MRAM for cache memory in order to keep overall application performance saving static power.

/pdf/exploration-of-magnetic-ram-based-memory-hierarchy-for-owb4916t77.pdf

Exploration of Magnetic RAM Based Memory Hierarchy for Multicore Architecture

Energy efficiency is a critical figure of merit for battery-powered applications. Today's embedded systems suffer from significant increase of power consumption essentially due to a high leakage current in advanced technology node. A significant portion of the total power consumption is spent into memory systems because of an increasing trend of embedded volatile memory area among the building components in System-on-Chips (SoCs). That is why new Non-Volatile Memory (NVM) technologies are considered as a potential solution to solve the energy efficiency issue. Among these NVM technologies, Magnetic RAM (MRAM) is a promising candidate to replace current memories since it combines non-volatility, high scalability, high density, low latency and low leakage. This paper explores use of MRAM into a memory hierarchy (from cache memory to register) of a processor-based system analyzing both performance and energy consumption.

https://hal-lirmm.ccsd.cnrs.fr/lirmm-01253332/document

Potential applications based on NVM emerging technologies

Nowadays, cryptography is widely used in many different devices (smartphones, tablets, computers, etc.). One of the most used cryptographic algorithms is AES (Advanced Encryption Standard). Crocus Technology is developing a technology called Match-In-Place TM (MIP). This is a memory based on comparison function. With this technology, data stored in the memory can be compared to an input data. The main expectation of this technology is that, during this comparison, no information leaks from the memory, which is interesting against side channel attacks. This assumption has been verified by simulation but not in practice yet. This paper proposes a new secure AES implementation based on the MIP technology. The use of this particular technology allows to protect the key in a secure environment to prevent attackers from retrieving it. MIP also allows a very low silicon area implementation of AES.

https://hal-lirmm.ccsd.cnrs.fr/lirmm-01421143/document

Bruno Mussard

Papers

Exploring MRAM Technologies for Energy Efficient Systems-On-Chip

Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture

Exploration of Magnetic RAM Based Memory Hierarchy for Multicore Architecture

Potential applications based on NVM emerging technologies

Implementation of AES Using NVM Memories Based on Comparison Function