The PASCAL Visual Object Classes Challenge

Massive multiple-input multiple-output (MIMO) is a key technology to meet the user demands in performance and quality of services (QoS) for next generation communication systems. Due to a large number of antennas and radio frequency (RF) chains, complexity of the symbol detectors increased rapidly in a massive MIMO uplink receiver. Thus, the research to find the perfect massive MIMO detection algorithm with optimal performance and low complexity has gained a lot of attention during the past decade. A plethora of massive MIMO detection algorithms has been proposed in the literature. The aim of this paper is to provide insights on such algorithms to a generalist of wireless communications. We garner the massive MIMO detection algorithms and classify them so that a reader can find a distinction between different algorithms from a wider range of solutions. We present optimal and near-optimal detection principles specifically designed for the massive MIMO system such as detectors based on a local search, belief propagation and box detection. In addition, we cover detectors based on approximate inversion, which has gained popularity among the VLSI signal processing community due to their deterministic dataflow and low complexity. We also briefly explore several nonlinear small-scale MIMO (2-4 antenna receivers) detectors and their applicability in the massive MIMO context. In addition, we present recent advances of detection algorithms which are mostly based on machine learning or sparsity based algorithms. In each section, we also mention the related implementations of the detectors. A discussion of the pros and cons of each detector is provided.

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Massive MIMO Detection Techniques: A Survey

It is well known that if each coefficient value of a digital filter is a sum of signed power-of-two (SPT) terms, the filter can be implemented without using multipliers. In the past decade, several methods have been developed for the design of filters whose coefficient values are sums of SPT terms. Most of these methods are for the design of filters where all the coefficient values have the same number of SPT terms. It has also been demonstrated recently that significant advantage can be achieved if the coefficient values are allocated with different number of SPT terms while keeping the total number of SPT terms for the filter fixed. In this paper, we present a new method for allocating the number of SPT terms to each coefficient value. In our method, the number of SPT terms allocated to a coefficient is determined by the statistical quantization step-size of that coefficient and the sensitivity of the frequency response of the filter to that coefficient. After the assignment of the SPT terms, an integer-programming algorithm is used to optimize the coefficient values. Our technique yields excellent results but does not guarantee optimum assignment of SPT terms. Nevertheless, for any particular assignment of SPT terms, the result obtained is optimum with respect to that assignment.

Signed Power-of-Two Term Allocation Scheme for the Design of Digital Filters

Although 4G (fourth generation) i.e. LTE (long term evolution) systems are now in use world-wide. But today’s 4G systems have some challenges left such as spectrum scarcity and energy efficiency. The prime objectives of near-by-future 5G (fifth generation) wireless communications are reliability, higher data rate, higher bandwidth, high spectrum efficiency, higher energy efficient and that too at lower latency. Channel coding tend to increase the reliability of the wireless communications system by adding extra bits in a controlled fashion and is considered to be most persuasive element of communication system. 4G LTE Turbo Codes have already been replaced by LDPC (low density parity check) Codes in many of the standards including mMTC (massive machine type communication), D2D (device to device communication) and URLLC (ultra-reliable low latency reliable communications). LDPC Codes and Polar Codes are securing much more observation because of their inherent advantages of excellent bit-error-rate performance, fast encoding and decoding procedures; which make them the strong contenders for 5G Channel Codes too. This paper provides the broad survey and comparison of the LDPC and Polar Codes along with their advantages and drawbacks which will aid in further improvement of the next generation wireless networks. In order to enlighten future research possibilities in this direction, issues addressed by distinct researchers have been explored too.

A survey on channel coding techniques for 5G wireless networks

The minimum-mean-square error (MMSE) plays a significant role in the signal detection process of massive multiple-input-multiple-output (MIMO) systems Matrix inversion, which is the major part of calculating the MMSE, suffers from high computing loads and low parallelism, especially in massive MIMO systems; as such, hardware implementation is difficult This paper proposes a user-level parallelism-based fully pipelined very large-scale integration (VLSI) architecture of an MMSE detector for an uplink $128\times 8~64$ -QAM massive MIMO system First, a diagonal-based systolic array with single-sided input is adopted; this array eliminates the throughput limitation Second, a weighted Jacobi-iteration-based architecture is proposed to iteratively achieve matrix inversion, thereby reducing the computational load and exploiting the potential parallelism of the matrix inversion Third, an approximated architecture is proposed to compute the log-likelihood ratio This architecture is verified on an FPGA and fabricated onto a 257 mm2 silicon with TSMC 65 nm CMOS technology, thereby achieving a 102 Gbps data rate at 680 MHz while dissipating 646 mW The results indicate an energy efficiency of 158 Gbps/W and an area efficiency of 040 Gbps/mm2, which are $293\times $ and $286\times $ that of state-of-the-art similar designs with CMOS technology, respectively

A 1.58 Gbps/W 0.40 Gbps/mm2 ASIC Implementation of MMSE Detection for $128\times 8~64$ -QAM Massive MIMO in 65 nm CMOS

This brief presents an efficient sorting architecture for successive-cancellation-list decoding of polar codes. In order to avoid performing redundant sorting operations on the metrics that are already sorted in the previous step of decoding, the proposed architecture separately processes the sorted metrics and unsorted ones. In addition, the odd–even sort network is adopted as a basic building block to further reduce the hardware complexity while sustaining low latencies for various list sizes. On average, the proposed architecture requires less than 50% of the compare-and-swap units demanded by the area-efficient sorting networks in the literature.

Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes

In this paper, we propose a low-complexity symbol detection algorithm for massive multiple-input multiple-output (MIMO) uplink. Grounded on the fact that a primary property of the massive MIMO systems guarantees the convergence of the Jacobi method, the method is exploited in the linear detection so that the estimate of transmitted symbols can be obtained without employing the computationally intensive matrix inversion. In addition, we propose a multiplication-free initial estimate for the Jacobi method in order to lessen the computational complexity further. Owing to the elimination of matrix inversion and the efficient initial estimate, the proposed algorithm achieves near-optimal error-rate performance with fewer computations than the state-of-the-art schemes.

Low-complexity symbol detection for massive MIMO uplink based on Jacobi method

Deep neural network (DNN)-based object detection has been investigated and applied to various real-time applications. However, it is hard to employ the DNNs in embedded systems due to their high computational complexity and deep-layered structure. Although several field-programmable gate array (FPGA) implementations have been presented recently for real-time object detection, they suffer from either low throughput or low detection accuracy. In this article, we propose an efficient computing system for real-time SSDLite object detection on FPGA devices, which includes novel hardware architecture and system optimization techniques. In the proposed hardware architecture, a neural processing unit (NPU) that consists of heterogeneous units, such as band processing, scaling, and accumulating, and data fetching and formatting units is designed to accelerate the DNNs efficiently. In addition, system optimization techniques are presented to improve the throughput further. A task control unit is employed to balance the workload and increase the utilization of heterogeneous units in the NPU, and the object detection algorithm is refined accordingly. The proposed architecture is realized on an Intel Arria 10 FPGA and enhances the throughput by up to $13.6\times $ compared to the state-of-the-art FPGA implementation.

Real-Time SSDLite Object Detection on FPGA

An efficient filter synthesis algorithm is proposed to minimize the number of adders required in the design of finite-impulse response filters. Given a specification, a filter can be synthesized by conducting two main steps: coefficient generation and multiplier-block synthesis. While most of previous works have focused on only one of the steps, the proposed algorithm integrates the two steps in an interleaved manner so as to take into account the effect of multiplier-block synthesis in generating coefficients. In addition, the concept of sensitivity is developed to reduce the complexity of computing the variable ranges of coefficients. Experimental results show that the proposed algorithm outperforms previous algorithms in terms of adder cost and takes a relatively short computation time.

FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis

This article presents an approximate signed digit representation (ASD) which quantizes the weights of convolutional neural networks (CNNs) in order to make multiplier-less CNNs without performing any retraining process. Unlike the existing methods that necessitate retraining for weight quantization, the proposed method directly converts full-precision weights of CNN models into low-precision ones, attaining accuracy comparable to that of full-precision models on the Image classification tasks without going through retraining. Therefore, it is effective in saving the retraining time as well as the related computational cost. As the proposed method simplifies the weights to have up to two non-zero digits, multiplication can be realized with only add and shift operations, resulting in a speed-up of inference time and a reduction of energy consumption and hardware complexity. Experiments conducted for famous CNN architectures, such as AlexNet, VGG-16, ResNet-18 and SqueezeNet, show that the proposed method reduces the model size by 73% at the cost of a little increase of error rate, which ranges from 0.09% to 1.5% on ImageNet dataset. Compared to the previous architecture built with multipliers, the proposed multiplier-less convolution architecture reduces the critical-path delay by 52% and mitigates the hardware complexity and power consumption by more than 50%.

Byeong Yong Kong

Papers

Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes

Low-complexity symbol detection for massive MIMO uplink based on Jacobi method

Real-Time SSDLite Object Detection on FPGA

FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis

Retrain-Less Weight Quantization for Multiplier-Less Convolutional Neural Networks