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Author

Byoung-June Kim

Bio: Byoung-June Kim is an academic researcher from Samsung. The author has contributed to research in topics: Layer (electronics) & Thin-film transistor. The author has an hindex of 12, co-authored 32 publications receiving 1490 citations.

Papers
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Patent
10 Apr 2008
TL;DR: In this paper, a method of manufacturing a thin-film transistor (TFT) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first pattern group, forming an amorphous silicon layer and an oxide semiconductor layer, and forming a protection layer including a contact hole on the second pattern group.
Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer, forming a protection layer including a contact hole on the second conductive pattern group, and forming a pixel electrode on the contact hole of the protection layer. The TFT substrate including the ohmic contact layer formed of an oxide semiconductor is further provided.

1,036 citations

Patent
24 Oct 2009
TL;DR: In this paper, a photoelectric conversion device having a semiconductor substrate (10) including a front side and back side, a protective layer (60), a non-single crystalline semiconductor layer (20), and a conductive layer (30), including the first impurity and a second impurity formed on a second portion of the back side of the first non-Single crystalline polysilicon (SLS) layer was presented.
Abstract: Disclosed herein is a photoelectric conversion device having a semiconductor substrate (10) including a front side and back side, a protective layer (60) formed on the front side of the semiconductor substrate (10), a first non-single crystalline semiconductor layer (20) formed on the back side of the semiconductor substrate, a first conductive layer (30) including a first impurity formed on a first portion of a back side of the first non-single crystalline semiconductor layer (20), and a second conductive layer (31) including the first impurity and a second impurity formed on a second portion of the back side of the first non-single crystalline semiconductor layer (20).

106 citations

Patent
22 Nov 2010
TL;DR: In this paper, a TFT array panel including a substrate, a gate line having a gate electrode, gate insulating layer formed on the gate line, a data line with a source electrode and a drain electrode spaced apart from the source electrode, a passivation layer formed between the data line and the drain electrode, and a pixel electrode connected to the drain electrodes is provided.
Abstract: A TFT array panel including a substrate, a gate line having a gate electrode, a gate insulating layer formed on the gate line, a data line having a source electrode and a drain electrode spaced apart from the source electrode, a passivation layer formed on the data line and the drain electrode, and a pixel electrode connected to the drain electrode is provided. The TFT array panel further includes a protection layer including Si under at least one of the gate insulating layer and the passivation layer to enhance reliability.

102 citations

Journal ArticleDOI
TL;DR: In this article, the material requirements of microcrystalline silicon (μc-Si) in terms of the device operation and configuration for thin film solar cells and thin film transistors (TFTs) were reviewed.

21 citations

Journal ArticleDOI
TL;DR: In this paper, a low-refractive-index and high-transmittance silicon oxide (SiO x ) with a mixed phase of n-type microcrystalline silicon was developed for intermediate reflector layers (IRLs) of high-efficiency amorphous Si and micro-crystaline-Si tandem solar cells, and the refractive index, crystalline fraction, and conductivity of the SiO x IRLs were characterized as functions of the deposition conditions.

20 citations


Cited by
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Patent
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

1,501 citations

Patent
25 Sep 2013
TL;DR: In this paper, a connection terminal portion is provided with a plurality of connection pads which are part of the connection terminal, each of which includes a first connection pad and a second connection pad having a line width different from that of the first one.
Abstract: An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

1,136 citations

Patent
11 Nov 2008
TL;DR: In this article, a plurality of openings having a minute contact area is provided instead of forming one penetrating opening having a large contact area to reduce a partial depression and also to ensure contact resistance.
Abstract: It is an object of the present invention to simplify steps needed to process a wiring in forming a multilayer wiring. In addition, when a droplet discharging technique or a nanoimprint technique is used to form a wiring in a contact hole having a comparatively long diameter, the wiring in accordance with the shape of the contact hole is formed, and the wiring portion of the contact hole is likely to have a depression compared with other portions. A penetrating opening is formed by irradiating a light-transmitting insulating film with laser light having high intensity and a pulse high in repetition frequency. A plurality of openings having a minute contact area is provided instead of forming one penetrating opening having a large contact area to have an even thickness of a wiring by reducing a partial depression and also to ensure contact resistance.

1,021 citations

Patent
04 Dec 2008
TL;DR: In this paper, a photoensitive material solution of a conductive film is selectively discharged by a droplet discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the region exposed to the laser light to be left and realizing a source wiring and a drain wiring having a more microscopic pattern than the pattern itself formed by discharging.
Abstract: The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the region exposed to laser light to be left and realizing a source wiring and a drain wiring having a more microscopic pattern than the pattern itself formed by discharging. One feature of the source wiring and the drain wiring is that the source wiring and the drain wiring cross an island-like semiconductor layer and overlap it.

1,001 citations

Patent
Jun-Hyung Souk1, Jeong-Young Lee1, Jong-Soo Yoon1, Kwon-Young Choi1, Bum-Ki Baek1 
23 Mar 2007
TL;DR: In this paper, a method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate, forming an gate insulating layer, forming a semiconductor layer, and forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion larger than the second portion.
Abstract: A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.

441 citations