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Byron L. Krauter
Researcher at IBM
Publications - 55
Citations - 2357
Byron L. Krauter is an academic researcher from IBM. The author has contributed to research in topics: Chip & Inductance. The author has an hindex of 22, co-authored 55 publications receiving 2331 citations.
Papers
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Journal ArticleDOI
When are transmission-line effects important for on-chip interconnections?
Alina Deutsch,Gerard V. Kopcsay,Phillip J. Restle,Howard H. Smith,George A. Katopis,Wiren D. Becker,Paul W. Coteus,C.W. Surovic,Barry J. Rubin,R.P. Dunne,T. Gallo,Keith A. Jenkins,L.M. Terman,Robert H. Dennard,George Anthony Sai-Halasz,Byron L. Krauter,D.R. Knebel +16 more
TL;DR: In this paper, the authors analyzed short, medium, and long on-chip interconnections having linewidths of 0.45-52 /spl mu/m in a five-metal-layer structure.
Journal ArticleDOI
A clock distribution network for microprocessors
Phillip J. Restle,Timothy G. McNamara,David A. Webber,Peter J. Camporese,K.F. Eng,Keith A. Jenkins,D.H. Allen,M.J. Rohn,M.P. Quaranta,David William Boerstler,Charles J. Alpert,C.A. Carter,R.N. Bailey,J.G. Petrovick,Byron L. Krauter,Bradley McCredie +15 more
TL;DR: A global clock distribution strategy implemented on several microprocessor chips is described, which consists of buffered, tunable tree networks, with the final trees all driving a common grid.
Journal ArticleDOI
On-chip wiring design challenges for gigahertz operation
Alina Deutsch,Paul W. Coteus,G.V. Kopcsay,Howard H. Smith,C.W. Surovic,Byron L. Krauter,Daniel C. Edelstein,P.L. Restle +7 more
TL;DR: This paper reviews the status of present day on-chip wiring design methodologies and understanding and design guidelines are given for using modeling and simulation techniques that have been previously used for package interconnections to teach designers how to make better use of available technologies.
Proceedings ArticleDOI
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals
TL;DR: It is proved that the Elmore delay is an absolute upper bound on the 50% delay of an RC tree response and that this bound holds for input signals other than steps, and that the actual delay asymptotically approaches theElmore delay as the input signal rise time increases.
Proceedings ArticleDOI
Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis
Byron L. Krauter,Sharad Mehrotra +1 more
TL;DR: This work proposes a rules-based method that efficiently and accurately captures the high and low frequency characteristics directly from layout shapes, and subsequently synthesizes a simple frequency independent ladder circuit suitable for timing analysis.