C.G. Sodini

Bio: C.G. Sodini is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Signal processing & Delta modulation. The author has an hindex of 3, co-authored 3 publications receiving 416 citations.

A higher order topology for interpolative modulators for oversampling A/D converters

Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

A slope adaptive delta modulator for VLSI signal processing systems

Abstract: A novel method of analog-to-digital (A/D) conversion utilizing a Slope Adaptive Delta Modulation approach which we will call Instantly Adaptive Delta Modulation (IADM), is described. This new system provides higher quality processable code than present modulators yet requires substantially reduced sampling rates. It displays a wide tolerance for variations in its component values and operates undisturbed in the presence of large amplitude dc or 60-Hz interference signals. An analysis of the frequency response and quantization noise characteristics of the system are presented. Specific designs for the component blocks demonstrate the compatibility of the system with present day CMOS technology. The compatibility of this system with VLSI technology makes it especially attractive for implementation in a monolithic audio-processing IC, such as a CODEC filter, or audio quality A/D converter.

A programmable demodulator for oversampled analog-to-digital modulators

Abstract: A programmable DSP (digital signal processor) architecture for use in an oversampled A/D (analog-to-digital) converter system is introduced. Based on this architecture, a set of synchronization equations for configuring the entire oversampled system for arbitrary speed-accuracy specifications is presented. The generality and simplicity of the architecture allow the reduction of this procedure to running high-level, user-friendly software and programming PROMs (programmable read-only memories). The architecture was implemented in a 2.0- mu m N-well CMOS technology. Fabricated samples demonstrated the ability to handle many applications, including 16 b of SNR (signal-to-noise ratio) for the digital audio (20-kHz baseband) and 18 b of SNR for voiceband (4-kHz baseband). It is concluded that this DSP architecture is the most general and efficient computation engine for FIR/IIR (finite impulse response/infinite impulse response) filtering of 1-b signals. It is capable of over 30 MIPs. The architecture's simplicity and flexibility facilitate its interfacing with a high-level, user-friendly software package. >

Understanding Delta-Sigma Data Converters

Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

An overview of sigma-delta converters

Abstract: Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

Quantization noise spectra

Abstract: Several results describing the behavior of quantization noise in a unified and simplified manner are discussed. Exact formulas for quantizer noise spectra are developed. They are applied to a variety of systems and inputs, including scalar quantization (PCM), dithered PCM, sigma-delta modulation, dithered sigma-delta modulation, two-stage sigma-delta modulation, and second-order sigma-delta modulation. >

A higher order topology for interpolative modulators for oversampling A/D converters

Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

An empirical study of high-order single-bit delta-sigma modulators

Abstract: Computer simulations are used to determine the stability limits of single-bit delta-sigma modulators up to order 8. It is found that none of the existing criteria for stability are adequate for design. Plots of the maximum signal-to-noise ratio (SNR) achievable with a given modulator order and oversampling ratio (OSR) are presented. These graphs can be used to determine the modulator order and OSR required to achieve a given SNR or to check the tightness of (as yet unavailable) theoretical bounds. >