By combining electrical, physical, and transport/atomistic modeling results, this study identifies critical conductive filament (CF) features controlling TiN/HfO2/TiN resistive memory (RRAM) operations. The leakage current through the dielectric is found to be supported by the oxygen vacancies, which tend to segregate at hafnia grain boundaries. We simulate the evolution of a current path during the forming operation employing the multiphonon trap-assisted tunneling (TAT) electron transport model. The forming process is analyzed within the concept of dielectric breakdown, which exhibits much shorter characteristic times than the electroforming process conventionally employed to describe the formation of the conductive filament. The resulting conductive filament is calculated to produce a non-uniform temperature profile along its length during the reset operation, promoting preferential oxidation of the filament tip. A thin dielectric barrier resulting from the CF tip oxidation is found to control filament resistance in the high resistive state. Field-driven dielectric breakdown of this barrier during the set operation restores the filament to its initial low resistive state. These findings point to the critical importance of controlling the filament cross section during forming to achieve low power RRAM cell switching.

Metal oxide resistive memory switching mechanism based on conductive filament properties

The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.

A comprehensive review on emerging artificial neuromorphic devices

Nanofabrication techniques for achieving dimensional control at the nanometer scale are generally equipment-intensive and time-consuming. The use of energetic beams of electrons or ions has placed the fabrication of nanopores in thin solid-state membranes within reach of some academic laboratories, yet these tools are not accessible to many researchers and are poorly suited for mass-production. Here we describe a fast and simple approach for fabricating a single nanopore down to 2-nm in size with sub-nm precision, directly in solution, by controlling dielectric breakdown at the nanoscale. The method relies on applying a voltage across an insulating membrane to generate a high electric field, while monitoring the induced leakage current. We show that nanopores fabricated by this method produce clear electrical signals from translocating DNA molecules. Considering the tremendous reduction in complexity and cost, we envision this fabrication strategy would not only benefit researchers from the physical and life sciences interested in gaining reliable access to solid-state nanopores, but may provide a path towards manufacturing of nanopore-based biotechnologies.

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Nanopore Fabrication by Controlled Dielectric Breakdown

Carbon nanotube devices offer intrinsic advantages for high-performance logic device applications. The ultrasmall body of a carbon nanotube-the tube diameter-is the key feature that should allow aggressive channel length scaling, while the intrinsic transport properties of the nanotube ensure at the same time high on-currents. In addition, the narrowness of the tube is critical to implementation of novel device concepts like the tunneling transistor. By understanding the unique capabilities of carbon nanotubes and using them in unconventional designs, novel nanoelectronic applications may become feasible. However, much better control of materials quality must be obtained, and new fabrication processes must be developed before such applications can be realized.

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Carbon Nanotubes for High-Performance Electronics—Progress and Prospect

The physical understanding of the programming and reliability mechanisms in resistive-switching memory devices requires a detailed characterization of the electrical and thermal conduction properties in the low-resistance state of the memory cell. The aim of this paper is the characterization of the conductive filament (CF), which controls the localized current flow in the low resistive state of the cell. Based on a new technique for evaluating the CF temperature during operation, we perform a statistical characterization of the critical filament temperature for the reset operation, i.e., the transition to the high-resistance state by the thermal dissolution of the CF. The thermal resistance of the CF and the activation energy for the dissolution mechanism are then evaluated, allowing for a physics-based numerical modeling of the reset operation based on CF thermal breakup.

Filament Conduction and Reset Mechanism in NiO-Based Resistive-Switching Memory (RRAM) Devices

In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during whi...

Dielectric breakdown mechanisms in gate oxides

Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well

Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

A physical model has been developed which complies with the experimental observation on the failure mechanism of ultrathin gate oxide breakdown during constant voltage stress. Dynamic equilibrium needs to be established between the percolation conductive path and the dielectric breakdown induced epitaxy (DBIE) formation during gate dielectric breakdown transient. The model is capable of linking the percolation model, soft breakdown, and hard breakdown to the DBIE growth for a variety of stress conditions and gate oxide thickness without involving new empirical parameters.

Percolation path and dielectric-breakdown-induced-epitaxy evolution during ultrathin gate dielectric breakdown transient

We present, for the first time, the monolithic integration of Gate-Ail-Around (GAA) Si-nanowire FETs into CMOS logic using top-down approach. The drive currents for N-and P-MOS transistors are matched using different number of channels for each to obtain symmetric pull-up and pull-down characteristics. Sharp ON-OFF transitions with high voltage gains (up to -45) are obtained which are best reported among the nanowire and carbon nanotube inverters. The inverters maintain their good transfer characteristics and noise margins for a wide range of VDD values, down to 0.2 V. Short circuit current at 0.2 V VDD is ~6 pA indicating excellent potential of these devices for low voltage and ultra low power applications. These results excel those reported in the literature for nanowire as well as FinFET (non-classical CMOS) inverters.

Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach

A novel method for realizing arrays of vertically stacked (e.g., times3 wires stacked) laterally spread out nanowires is presented for the first time using a fully Si-CMOS compatible process. The gate-all-around (GAA) MOSFET devices using these nanowire arrays show excellent performance in terms of near ideal sub-threshold slope (<70 mV/dec), high Ion/Ioff ratio (~107), and low leakage current. Vertical stacking economizes on silicon estate and improves the on-state IDSAT at the same time. Both n- and p-FET devices are demonstrated

C.H. Tung

Papers

Dielectric breakdown mechanisms in gate oxides

Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

Percolation path and dielectric-breakdown-induced-epitaxy evolution during ultrathin gate dielectric breakdown transient

Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach

Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs