C.J.J. Dachs

Bio: C.J.J. Dachs is an academic researcher from Philips. The author has contributed to research in topics: CMOS & MOSFET. The author has an hindex of 5, co-authored 22 publications receiving 75 citations.

A 0.13 /spl mu/m poly-SiGe gate CMOS technology for low-voltage mixed-signal applications

Abstract: We present here a novel approach to CMOS fabrication based on advanced lateral channel doping profiling technique coupled to gate workfunction engineering. The performance of this technology for both digital and analog applications is evaluated in detail to illustrate that it satisfies the requirements for mixed digital-analog circuitry. The use of asymmetric source/drain lateral profiles proves to be especially beneficial to analog applications.

Ultra-thin oxynitride gate dielectrics by pulsed-RF DPN for 65 nm general purpose CMOS applications

Abstract: This paper investigates the use of pulsed-RF decoupled plasma nitridation (DPN) for the growth of oxynitride gate dielectrics for 65 nm general purpose (GP) applications. The effects of several DPN plasma parameters, base oxide thickness and post-nitridation anneal (PNA) conditions on device performance were evaluated. Significant gate leakage reduction and improved trade-off between the equivalent-oxide-thickness (EOT) and mobility, for scaled EOT, have been found in devices with oxynitrides grown from thicker base oxides and optimized DPN/PNA processing conditions. DPN oxynitrides with 1.1-1.4 nm EOT have maximum operating voltages above 0.8 V, as extrapolated for a 10 year lifetime.

RPN Oxynitride Gate Dielectrics for 90 nm Low Power CMOS Applications

Abstract: This paper investigates the use of RPN-based oxynitride gate dielectrics for 90 nm Low Power (LP) CMOS applications. Several recipes have been developed to optimise the gate dielectric for targeted EOT, high mobility and improved EOT uniformity. Compared to conventional furnace oxynitride, significant gate leakage reduction has been found in devices with plasma nitrided oxides. This enabled reaching the spec for the IOFF current of 20 pA/ µm and improve the ION-IOFF trade-off. The ION current obtained at 1.2 V for NMOS and PMOS devices is 427 µA/µ m( at IOFF =16 pA/µm) and 170 µA/µ m( at I OFF =16 pA/µm), respectively. The obtained results are among the best values reported in the literature.

Method of manufacturing a semiconductor device having a pocket implant in channel region

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor body ( 1 ) of a first conductivity type which is provided at a surface ( 2 ) with a transistor having a gate ( 28 ) insulated from a channel ( 13 ) provided at the surface ( 2 ) of the semiconductor body ( 1 ) by a gate dielectric ( 26 ), a structure is provided on the surface ( 2 ) comprising a dielectric layer ( 14 ) having a recess ( 16 ), which recess ( 16 ) is aligned to a source zone ( 11,9 ) and a drain zone ( 12,9 ) of a second conductivity type provided at the surface ( 2 ) of the semiconductor body ( 1 ) and has side walls ( 17 ) extending substantially perpendicularly to the surface ( 2 ) of the semiconductor body ( 1 ). In this recess ( 16 ), a double-layer ( 20 ) is applied consisting of a second sub-layer ( 19 ) on top of a first sub-layer ( 18 ), which second sub-layer ( 19 ) is removed over part of its thickness until the first sub-layer is exposed, which first sub-layer ( 18 ) is selectively etched with respect to the second sub-layer ( 19 ) and the side walls ( 17 ) of the recess ( 16 ) to a depth, thereby forming trenches ( 21 ) extending substantially perpendicularly to the surface ( 2 ) of the semiconductor body ( 1 ). Via these trenches ( 21 ) impurities of the first conductivity type are introduced into the semiconductor body ( 1 ), thereby forming pocket implants ( 22 ).

Advanced PMOS Device Architecture for Highly-Doped Ultra-Shallow Junctions

Abstract: In this paper we study the integration of Boron ultra-shallow junctions (USJ) obtained by Germanium pre-amorphization, Fluorine co-implantation and fast ramp-up and ramp-down anneals into advanced p-channel metal-oxide-semiconductor (PMOS) devices. Several integration issues associated to these USJ are investigated: short-channel effects control, implantation tilt angle influence, junction de-activation, thermal budget, silicide process. We show that remarkable PMOS device performance enhancement (Ion=450 µA/µm at Ioff=250 nA/µm for devices with Lg\cong50 nm) can be achieved when full potential of highly-active and abrupt USJ is exploited by combining it with a low thermal budget integration scheme and a low contact resistance NiSi.

Analog Circuit Design in Nanoscale CMOS Technologies

Abstract: As complementary metal-oxide-semiconductor (CMOS) technologies are scaled down into the nanometer range, a number of major nonidealities must be addressed and overcome to achieve a successful analog and physical circuit design. The nature of these nonidealities has been well reported in the technical literature. They include hot carrier injection and time-dependent dielectric breakdown effects limiting supply voltage, stress and lithographic effects limiting matching accuracy, electromigration effects limiting conductor lifetime, leakage and mobility effects limiting device performance, and chip power dissipation limits driving individual circuits to be more energy-efficient. The lack of analog design and simulation tools available to address these problems has become the focus of a significant effort with the electronic design automation industry. Postlayout simulation tools are not useful during the design phase, while technology computer-aided design physical simulation tools are slow and not in common use by analog circuit designers. In the nanoscale era of analog CMOS design, an understanding of the physical factors affecting circuit reliability and performance, as well as methods of mitigating or overcoming them, is becoming increasingly important. The first part of the paper presents factors affecting device matching, including those relating to single devices as well as local and long-distance matching effects. Several reliability effects are discussed, including physical design limitations projected for future downscaling. In some cases, it may be helpful to exceed foundry-specified drain-source voltage limits by a few hundred millivolts. Models are presented for achieving this, which include the dependence on the shape of the output waveform. The condition Vsb > 0 is required for cascode circuit configurations. The role of other terminal voltages is discussed, as Vsb > 0 increases both hot and cold carrier damage effects in highly scaled devices. The second part of the paper focuses on trends in device characteristics and how they influence the design of nanoscale analog CMOS circuits. A number of circuit design techniques employed to address the major nonidealities of nanoscale CMOS technologies are discussed. Examples include techniques for establishing on-chip accurate and temperature-insensitive bias currents, digital calibration of analog circuits, and the design of regulator and high-voltage circuits. Achieving high energy efficiency in ICs capable of accommodating 109 devices is becoming critically important. This paper also presents a survey of the evolution of figure of merit for analog-to-digital converters.

CMOS image sensor and method for fabricating the same

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same are disclosed. The image sensor includes a sub-layer having a photodiode and a plurality of transistors formed thereon, a pad insulating layer formed on the sub-layer, a micro-lens formed on the pad insulating layer, the micro-lens including a first insulating layer having an uneven surface and a second insulating layer covering upper and side surfaces of a projected portion of the first insulating layer to form a dome shape, and a planarization layer formed on the micro-lens, and a color filter formed on the planarization layer.

Overview of the impact of downscaling technology on 1/f noise in p-MOSFETs to 90 nm

Abstract: An overview of theoretical 1/f noise models is given. Analytical expressions showing the device geometry and bias dependencies of 1/f noise in all conduction regimes are summarised. Novel experimental studies on 1/f noise in MOS transistors are presented with special emphasis on p-channel transistors from 90 nm CMOS technology. In addition to the noise in the drain terminal, the gate current noise is investigated because the gate insulator is very thin and significant gate leakage current appears at high gate biases. In the subthreshold regime, the drain current noise agrees with the /spl Delta/N model, whereas in strong inversion the evolutions of the noise level can be described by Hooge's empirical relation. The gate current noise shows 1/f and white noise components. The white noise is very close to shot noise and the 1/f noise component is almost a quadratic function of the gate leakage current. Coherence measurements reveal that the increase of drain noise at high gate biases can be attributed to tunnelling effects in the gate insulator. Both the input-referred (gate) noise and the slow oxide trap density can be used as a figure of merit of the low-frequency noise in MOSFETs.

Emerging silicon-on-nothing (SON) devices technology

Abstract: In this paper we explain the advantages of very thin layers (in the channel and in the BOX) of the silicon-on-nothing (SON) transistors. Electrical results are also presented, with gate length down to 38 nm, with a conduction channel thickness as thin as 9 and 5 nm. It is also demonstrated that SON is better suited than bulk for accepting a metallic gate for low-voltage operation due to its intrinsic low threshold voltage. We have integrated midgap CoSi 2 metal gate by total gate silicidation on SON transistors with Si-conduction channel thickness down to 5 nm. Finally, we will analyse the ITRS’01 CMOS Roadmap and show that SON allows reaching the I on / I off specifications down to the 32 nm node and approaching closely those for the 22 nm node, that is by far impossible with bulk.

Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications

Abstract: Scaling of analog CMOS in the deep submicron regime is challenging, particularly for mixed mode system on chip applications due to the tradeoff in design requirements for analog and digital applications. The conventional approach employing aggressive gate oxide and S/D junction scaling to suppress the two-dimensional (2-D) electrostatic coupling and related short channel effects that degrade the device behavior in the deep submicron regime, though, improves the digital performance. However, this approach is not sufficient to obtain a reasonable analog performance. This paper presents a comprehensive study on the analog performance of scaled MOSFETs and explores alternative ways for improving the analog performance of these devices. It is shown that an easily integrable innovative channel engineering scheme in the form of single pocket structures can be used in the standard logic CMOS process to significantly improve the device analog performance of the deep submicron devices.