C. Jones

Bio: C. Jones is an academic researcher from University of California, Los Angeles. The author has contributed to research in topics: Low-density parity-check code & Turbo code. The author has an hindex of 5, co-authored 5 publications receiving 687 citations.

Selective avoidance of cycles in irregular LDPC code construction

Abstract: This letter explains the effect of graph connectivity on error-floor performance of low-density parity-check (LDPC) codes under message-passing decoding A new metric, called extrinsic message degree (EMD), measures cycle connectivity in bipartite graphs of LDPC codes Using an easily computed estimate of EMD, we propose a Viterbi-like algorithm that selectively avoids small cycle clusters that are isolated from the rest of the graph This algorithm is different from conventional girth conditioning by emphasizing the connectivity as well as the length of cycles The algorithm yields codes with error floors that are orders of magnitude below those of random codes with very small degradation in capacity-approaching capability

Construction of irregular LDPC codes with low error floors

Abstract: This work explains the relationship between cycles, stopping sets, and dependent columns of the parity check matrix of low-density parity-check (LDPC) codes. Furthermore, it discusses how these structures limit LDPC code performance under belief propagation decoding. A new metric called extrinsic message degree (EMD) measures cycle connectivity in bipartite graph. Using an easily computed estimate of EMD, we propose a Viterbi-like algorithm that selectively avoids cycles and increases stopping set size. This algorithm yields codes with error floors that are orders of magnitude below those of girth-conditional codes.

Reduced complexity MIMO detectors for LDPC coded systems

Abstract: We consider the performance and complexity analysis of low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) systems with reduced complexity detectors in fast Rayleigh fading channels. We use a turbo iterative detection-and-decoding receiver which combines a soft MIMO demodulator and a message-passing LDPC decoder We examine three low complexity detectors: minimum mean-square error (MMSE) with soft interference cancellation (SIC), MMSE suppression, and MMSE with hard decision interference cancellation (MMSE-HIC). We compare the performance and complexity of these detectors with the standard soft maximum a posteriori (MAP) detector and show that they provide a lower computational complexity with only a small penalty in performance (/spl sim/0.5 dB). We also provide comparisons with the Shannon capacity limits for ergodic multiple-antenna channels and show that an LDPC coded system using a length 15,000 code and QPSK modulation with reduced-complexity detection operates 2 and 3 dB from the ergodic capacity of the Rayleigh MIMO channel.

The universality of LDPC codes on wireless channels

Abstract: Root and Variaya proved the existence of codes that can communicate reliably over any linear Gaussian channel for which the mutual information exceeds the information rate of the code. In this paper we demonstrate that properly designed low-density parity-check (LDPC) codes are such codes and that their performance lies in close proximity to the Root and Variaya capacity for the linear Gaussian vector channels (a.k.a. space-time channels). We also demonstrate the robustness of the codes on the partial-band jamming channel and in fast Rayleigh fading.

Robustness of LDPC codes on periodic fading channels

Abstract: Root and Variya (1968) proved the existence of codes that can communicate reliably over any member of a set of linear Gaussian channels where each member exceeds a given amount of mutual information. In this paper we show that LDPC codes are such codes and that their performance lies within 0.1 bits of the Root and Variya capacity for a large family of periodic Gaussian channels. specifically, the robustness of LDPC codes to periodic fading is demonstrated through the consistency of their mutual information performance across period-2 and period-256 fading profiles. The latter case implies that these codes are ideal candidates for coding in OFDM.

Regular and irregular progressive edge-growth tanner graphs

Abstract: We propose a general method for constructing Tanner graphs having a large girth by establishing edges or connections between symbol and check nodes in an edge-by-edge manner, called progressive edge-growth (PEG) algorithm. Lower bounds on the girth of PEG Tanner graphs and on the minimum distance of the resulting low-density parity-check (LDPC) codes are derived in terms of parameters of the graphs. Simple variations of the PEG algorithm can also be applied to generate linear-time encodeable LDPC codes. Regular and irregular LDPC codes using PEG Tanner graphs and allowing symbol nodes to take values over GF(q) (q>2) are investigated. Simulation results show that the PEG algorithm is a powerful algorithm to generate good short-block-length LDPC codes.

Broadband MIMO-OFDM wireless communications

Abstract: Orthogonal frequency division multiplexing (OFDM) is a popular method for high data rate wireless transmission. OFDM may be combined with antenna arrays at the transmitter and receiver to increase the diversity gain and/or to enhance the system capacity on time-varying and frequency-selective channels, resulting in a multiple-input multiple-output (MIMO) configuration. The paper explores various physical layer research challenges in MIMO-OFDM system design, including physical channel measurements and modeling, analog beam forming techniques using adaptive antenna arrays, space-time techniques for MIMO-OFDM, error control coding techniques, OFDM preamble and packet design, and signal processing algorithms used to perform time and frequency synchronization, channel estimation, and channel tracking in MIMO-OFDM systems. Finally, the paper considers a software radio implementation of MIMO-OFDM.

Error Floors of LDPC Codes

Abstract: We introduce a computational technique that accurately predicts performance for a given LDPC code in the error floor region. We present some results obtained by applying the technique and describe certain aspects of it.

Block-LDPC: a practical LDPC coding system design approach

Abstract: This paper presents a joint low-density parity-check (LDPC) code-encoder-decoder design approach, called Block-LDPC, for practical LDPC coding system implementations. The key idea is to construct LDPC codes subject to certain hardware-oriented constraints that ensure the effective encoder and decoder hardware implementations. We develop a set of hardware-oriented constraints, subject to which a semi-random approach is used to construct Block-LDPC codes with good error-correcting performance. Correspondingly, we develop an efficient encoding strategy and a pipelined partially parallel Block-LDPC encoder architecture, and a partially parallel Block-LDPC decoder architecture. We present the estimation of Block-LDPC coding system implementation key metrics including the throughput and hardware complexity for both encoder and decoder. The good error-correcting performance of Block-LDPC codes has been demonstrated through computer simulations. With the effective encoder/decoder design and good error-correcting performance, Block-LDPC provides a promising vehicle for real-life LDPC coding system implementations.