C. M. Tang

Bio: C. M. Tang is an academic researcher from Universiti Tunku Abdul Rahman. The author has contributed to research in topics: MPSoC & System on a chip. The author has an hindex of 3, co-authored 7 publications receiving 20 citations.

A reconfigurable and scalable verification environment for NoC design

Abstract: A flexible verification environment is introduced that is adaptive for the corresponding NoC architecture. We will describe the method using the Universal Verification Methodology (UVM) to create a reconfigurable and scalable platform to facilitate the early verification and validation of the NoC system.

Virtual Prototyping Platform for Multiprocessor System-on-Chip Hardware/Software Co-design and Co-verification

Abstract: This paper describes the implementation of a virtual prototyping platform to address the ever-challenging multiprocessor system-on-chip (MPSoC) hardware/software co-design and co-verification requirements The increasingly popular deployment of MPSoC brings complexity to system modeling, design, and verification Fiercely competitive business environment makes it absolutely critical to rein in time-to-market and chip fabrication costs The holy grail is to be able to verify the hardware design and synthesize to the gate level for physical layout, at the same time carry out software development for the hardware design using the same system models and verification platforms One approach is to raise the abstraction level of system design and verification to ESL In this paper, a virtual prototyping platform is built using SystemC with transaction-level modeling (TLM) and the open virtual platforms (OVP) processor model with instruction set simulator (ISS) As a demonstration of concept and feasibility, the virtual platform prototypes a 128-bit advanced encryption standard (AES) Cryptosystem MPSoC The supporting subsystems and environment are also modeled, for example the system peripherals, the network-based interconnect scheme or Network-on-Chip (NoC), system firmware, the interrupt service handling, and driver The virtual platform is scalable up to but not limited to twelve processing elements and configurable to the extent of the OVPs generic memory models (RAM and ROM) addresses and sizes, simulation parameters and debugging and tracing options

A scalable bootloader and debugger design for an NoC-based multi-processor SoC

Abstract: This paper presents bootloader and debugger architectures that are designed for an NoC-based Multiprocessor System On-Chip (MPSoC). An MPSoC demands scalable bootloader and debugger architectures, especially with the increasing of the number of the processor cores. The proposed bootloader and debugger designs utilize the NoC interconnect network to distribute data to and from the cores. With this design approach, the bootloader and debugger require relatively small hardware overhead and are able to fully utilize the benefit of the NoC architecture's scalability.

A scalable and configurable Multiprocessor System-on-Chip (MPSoC) virtual platform for hardware and software co-design and co-verification

Abstract: This paper defines a scalable and configurable Multiprocessor System-on-Chip virtual platform for hardware and software co-design and co-verification in Electronic System Level (ESL) design. It includes the integration of an Instruction Set Simulator (ISS) to the virtual platform, Transaction Level Modeling (TLM), IP (Intellectual Property) block design in high level of abstraction, and hardware and software partitioning. The virtual platform has been tested to develop and successfully tested to develop and run an AES-128 encryption software. The architecture of the virtual platform consist of multiple ARM Cortex-M0 processor, bus-based and Mesh NoC (Network-on-Chip) architecture, and IP (peripherals) to support the system. Lotus-G displays its capability to fill the gap between hardware and software team in ESL design and verification flow. It provides the software team with a platform which enables them to start software development and testing early before the RTL platform is ready. The virtual platform also gives the hardware team a golden reference model that acts as the functional specification reference during hardware design and verification.

Exploring software-defined radio on Multi-Processor System-on-Chip

Abstract: Sofware-Defined Radio (SDR) has been proposed as a solution for a single device to overcome various and changing radio standards. It allows wide range of computational device, such as personal computer processor and Multi-Processor System-on-Chip (MPSoC) to function as radio baseband processor. Number of works of SDR implementation on MPSoC has been done, variously differing according to underlying hardware platform. Main reason is to utilize the hardware architecture, providing power efficiency and effective processing. This paper explores idea of utilizing RUMPS401 chip, an ARM based heterogeneous MPSoC designed by Universiti Tunku Abdul Rahman VLSI Center, as a baseband processor based on its architecture. A workflow of implementing SDR on ARM based MPSoC using Matlab and ARM Keil Development Tools is also proposed here. The implementation and testing of the proposed idea is still an ongoing work.

A reusable verification environment for NoC platforms using UVM

Abstract: Network on Chip (NoC) has emerged as an interconnection solution for the modern digital systems, especially for System on Chip (SoC), due to the large number of IPs in the system that need to communicate. Various systems and routers have been introduced; hence the need to make a reusable verification environment to test both single routers and networks. In this paper, we propose a reusable verification environment for NoC platforms using the Universal Verification Methodology (UVM) that tests and verifies both routers and networks in an easily modifiable manner to fit various routers and networks. The environment also evaluates performance parameters such as injection rate, throughput and latency.

Contribution à l'amélioration des plateformes virtuelles SystemC/TLM : configuration, communication et parallélisme

Abstract: Le marche de l’Internet des Objets (IdO) est en pleine progression. Il va continuer a croitre et a se developper a un rythme soutenu dans les prochaines annees. Les objets connectes sont constitues de composants electroniques dedies, de processeurs et de codes logiciels. La conception de tels systemes constitue aujourd’hui un challenge au niveau industriel. Ce challenge est renforce par la concurrence du marche et le delai de commercialisation qui impactent directement sur le developpement d’un systeme. Le processus de conception actuel consiste en l’elaboration d’un cahier des charges. Dans un premier temps, l’equipe en charge du developpement materiel commence a developper le produit. Ensuite, la partie applicative peut etre mise au point par les developpeurs logiciels. Une fois le premier prototype materiel disponible, l’equipe logicielle peut alors integrer sa partie et tenter de la valider fonctionnellement. Cette etape peut mettre en lumiere des defauts dans le logiciel mais aussi lors de la conception materielle. Malheureusement,la decouverte ce type d’erreurs intervient beaucoup trop tard dans le processus de conception retardant la commercialisation du systeme. Afin de securiser au plus tot les developpements materiel et logiciel, des methodologies basees sur le standard SystemC/Transaction Level Modeling (TLM) ont ete proposees. Elles permettent de modeliser et de simuler du materiel. Durant les phases amont de conception d’un systeme, elles permettent de mettre en commun une version virtuelle du (futur) systeme entre les equipes logicielle et materielle. Cette version virtuelle est plus couramment appelee plateforme virtuelle. Elle permet de tester et de valider le plus tot possible lors du cycle de conception, de reduire le cout materiel en limitant la fabrication de prototypes, mais aussi de gagner du temps et donc de l’argent en diminuant les risques. Or, les objets integrent de plus en plus de fonctionnalites aux niveaux materiel et logiciel. Les besoins ayant evolue, le standard de simulation SystemC/TLM ne repond plus a l’heure actuelle a toutes les attentes. Ces attentes concernent plus particulierement les aspects lies a la simulation de systemes composes de nombreuses fonctionnalites, de protocoles de communication disparates mais aussi de modeles complexes et consommateur de temps pendant la simulation. Des activites de recherche ont deja ete menees sur ces sujets. Cependant, elles ont pour la plupart abouti a des solutions qui ne sont pas interoperables. Les solutions existantes ne permettent donc pas de beneficier de la reutilisation des modeles de la litterature. Afin de repondre a ces problemes,une solution permettant la configuration de modeles SystemC/TLM a ete recherchee. Cette derniere fait desormais partie du standard Configuration, Control and Inspection (CCI). Dans un second temps, la modelisation de protocoles de communication a un haut niveau d’abstraction(TLM Loosely Timed (LT) et Approximately Timed (AT)) a ete etudiee, et plus precisement des protocoles de type non bus. Une evolution du standard actuel permettant d’ameliorer le support,l’interoperabilite, la reutilisation a ete proposee dans le cadre de la these. Ensuite, une evolution du standard SystemC et plus precisement du comportement du noyau de simulation a ete etudiee pour supporter l’attente d’evenements asynchrones. Ce type d’evenement ouvre la voie a la parallelisation et la distribution de modeles sur differents threads / machines. Enfin, une solution permettant l’integration de modeles de Central Processing Units (CPU) integres dans QuickEMUlator (QEMU), un emulateur / virtualisateur de systeme, a ete etudiee. Finalement, toutes ces contributions ont ete associees a travers la modelisation d’un ensemble d’objets connectes a une passerelle.

Generic Bootloader Architecture Based on Automatic Update Mechanism

Abstract: Bootloader transplantation and update is a necessary process for each embedded system development. Due to the complex architecture and strong hardware dependency of the bootloader, the development cost is wasted. In this paper, we use the modular design of the code and custom instructions to reduce the workload of the transplant, use the macro definition file to achieve the online update. At the same time set up a backup for the flash memory area to increase the reliability. Implementing this bootloader on the general-purpose platform PowerPC reduces the migration process by more than 60% compared with U-Boot. The bootloader can be started from the backup area with a success rate of 92.5% or more.

A narrative of UVM testbench environment for interconnection routers: A practical approach

Abstract: In contrast to past projections using conventional bus-based interconnections, the use of Network on Chip (NoC) as an interconnection platform has become more promising to solve complex on-chip communication problems due to what it offers from scalability, reusability and efficiency. Moreover, providing a suitable test base to inspect and verify functionality of any IP core is a compulsory stage. To elaborate; Universal Verification Methodology (UVM) is introduced as a standardized and reusable methodology for verifying integrated circuit designs. In this paper, we present an architecture of a complete UVM environment to test generic routers through various test cases providing different scenarios to be applied. We also aim to establish a base on which other researchers can build to proceed towards finding better solutions.