C Prayline Rajabai
Bio: C Prayline Rajabai is an academic researcher from VIT University. The author has contributed to research in topics: Deblocking filter & Codec. The author has an hindex of 2, co-authored 3 publications receiving 6 citations.
TL;DR: An efficient architecture for deblocking filter used to smoothen the pixels of the decompressed video data is proposed, which utilizes both pipelining and parallelism.
Abstract: With the increasing demand in electronic gadgets expecting better video quality for multimedia applications, various coding standards evolved for the past two decades and optimization on the architectures of the various modules used in the video codec is most popular. In this paper, an efficient architecture for deblocking filter used to smoothen the pixels of the decompressed video data is proposed, which utilizes both pipelining and parallelism. The filtering process follows a sequential order as filtering vertical edges of luma block and chroma block followed by the horizontal edges of the luma block and chroma block. Three pipeline stages are used and four edges, either vertical or horizontal are filtered in parallel. Internal buffers which hold the sub-blocks read from the external frame buffers are accessed in a ping pong fashion to filter the adjacent sub-edges and thus reducing the external memory access cycles. Due to parallelism with novel edge filtering order, self-transposing mechanism, and ping pong buffer access, the throughput is increased. The proposed quad parallel edge deblocking filter architecture is implemented using Synopsys 90 nm library. It achieves a target area of 19.8 K and can process a Macro Block in 58 clock cycles.
01 Jul 2017TL;DR: High throughput hardware architecture designed to calculate the Sum of Absolute Difference (SAD) based on the variable block size of the image using Comparator and Carry skip adder unit improves the performance of SAD calculation in terms of speed, area, and power.
Abstract: In this paper, the high throughput hardware architecture is designed to calculate the Sum of Absolute Difference (SAD) based on the variable block size of the image. Even though the fixed block size motion estimation is simple with respect to the complexity of the variable block size motion estimation, variable block size estimation technique results in exquisite performance. Motion estimation is a crucial module/block which plays a major role in computing the efficiency of video coding. Because of variable block size in H.264, motion estimation becomes more complex and requires most efficient hardware for implementation in real-time video coding. The hardware implementation of SAD is done using Comparator and Carry skip adder. The comparator is used to implement the absolute difference unit, which is used to calculate the absolute difference values between each pixel of the current frame and the reference frame. Carry skip adder is used to add all the output values of the absolute difference unit. Carry skip adder improves the performance of the arithmetic operation. It does not wait for carrying to propagate which helps in increasing the speed of operation of adding. Comparator and Carry skip adder unit improves the performance of SAD calculation in terms of speed, area, and power. We had also proposed a control unit for H.264 video. This proposed control unit calculates the SAD output values according to block size given as input to control unit.
TL;DR: In this paper, the authors present an intricate analysis of various hardware architectures of deblocking filters used for H.264 and H.265 coding standards and present an efficient hardware implementation of the deblocking filter is essential for high-resolution video applications such as HDTV to increase the decoding throughput, to achieve high speed and to reduce the off-chip memory access cycles.
Abstract: H.264 and H.265 are the most popular video coding standards used for various applications. These coding standards use multiple modules to perform video compression. Among the various modules, the deblocking filter (DBF) is one of the critical modules in the video codec, which requires extensive computation. It is computationally complicated and critically time-consuming. DBF removes the blocking artefacts caused due to inverse transform, intra-prediction, inter-frame prediction and motion compensated prediction. For the past two decades, the deblocking filtering algorithm is implemented in hardware and research is still going on for realising optimised hardware solutions for this critical module. Efficient hardware implementation of the DBF is essential for high-resolution video applications such as HDTV to increase the decoding throughput, to achieve high speed and to reduce the off-chip memory access cycles. This paper presents an intricate analysis of various hardware architectures of DBF used for H.264 and H.265 coding standards.
TL;DR: A hardware-efficient implementation of integrated deblocking filter (DBF) and sample adaptive offset (SAO) parameter estimation architecture for 16 × 16, 32 × 32, and 64 × 64 coding tree units (CTU) in HEVC that delivers rate–distortion performance comparable to the HEVC standard.
01 Feb 2021TL;DR: In this paper, a dual standard deblocking filter is proposed for both AVC and HEVC, which enables four edges to be processed simultaneously and reduces the number of clock cycles needed for processing.
Abstract: Advanced Video Coding (AVC) also known as H.264 is a popular video coding standard which is used in many image processing applications. In order to fulfill the increasing demand for better video quality with less complex designs, High Efficiency Video Coding (HEVC) also known as H.265 came into picture. HEVC provides better quality with half the bit rate required for processing in comparison with AVC. In case of AVC, the design of deblocking filter is more complex due to the filtering decisions, whereas HEVC is less complex and also supports parallel processing. As there is a need for high throughput and less complex deblocking filter, a novel dual standard deblocking filter is proposed in this work which supports both AVC and HEVC. In particular, a novel filtering order which enables four edges to be processed simultaneously has been proposed for both AVC and HEVC. For AVC, the proposed design takes 18 clock cycles to process a 16 × 16 macroblock and for HEVC standard, the proposed design takes 12 clock cycles to process a 16 × 16 coding transform unit (CTU). In addition to this, the proposed design supports parallel processing concept in HEVC. The proposed design is synthesized using Xilinx ISE 14.7 and is mapped to xc5vlx30-1ff324 Virtex-5 Field programmable gate array (FPGA). Thus it helps in increasing the execution speed of the design and it is also noted that there is a reduction in number of clock cycles needed for processing when compared with the existing architectures. The physical implementation of the proposed architecture is also carried out using Semiconductor Lab (SCL) 180 nm process node.
TL;DR: This paper combines the advantages of Edge-Preserved Filtering (EPF) and Bidirectional Motion Estimation (BME) in an attempt to reduce the computational complexity of Frame Rate Up-Conversion (FRUC).
Abstract: The improvement of resolution of digital video requires a continuous increase of computation invested into Frame Rate Up-Conversion (FRUC). In this paper, we combine the advantages of Edge-Preserved Filtering (EPF) and Bidirectional Motion Estimation (BME) in an attempt to reduce the computational complexity. The inaccuracy of BME results from the existing similar structures in the texture regions, which can be avoided by using EPF to remove the texture details of video frames. EPF filters out by the high-frequency components, so each video frame can be subsampled before BME, at the same time, with the least accuracy degradation. EPF also preserves the edges, which prevents the deformation of object in the process of subsampling. Besides, we use predictive search to reduce the redundant search points according to the local smoothness of Motion Vector Field (MVF) to speed up BME. The experimental results show that the proposed FRUC algorithm brings good objective and subjective qualities of the interpolated frames with a low computational complexity.
01 Aug 2018
TL;DR: This paper proposes an optimization of SAD units considering the state-of-the-art High Efficiency Video Coding (HEVC) standard, which avoids the computation of candidates that will surely not be selected in the IME search, by applying Partial Distortion Elimination (PDE).
Abstract: Integer Motion Estimation (IME) is an important tool that explores the temporal redundancies in video encoders. It stands out among the most time-consuming and memory intensive tasks in the encoding process. Most of the IME processing is spent on the computation of similarities between pixel blocks, usually using the Sum of Absolute Differences (SAD) as block selection criterion. Designing high-throughput and energy-efficient SAD units is an effective way of increasing the performance of IME architectures. This paper proposes an optimization of SAD units considering the state-of-the-art High Efficiency Video Coding (HEVC) standard, which avoids the computation of candidates that will surely not be selected in the IME search, by applying Partial Distortion Elimination (PDE). The method achieves, without any loss in coding performance, an average reduction of 16.41% and 11.64% in the energy consumption for 1080p and 2160p (4K) videos, respectively, when compared to an HEVC SAD implementation without PDE.
01 Jan 2021TL;DR: In this paper, authors have studied those existing security protocols to propose a secured audio and video conferencing system through wired and wireless network with control and command of all the resources with the actual user only, to de-escalate and arrest the access of adversary over the resources of user.
Abstract: The recent outbreak of global pandemic of coronavirus (COVID-19) has shown us a wide scope of improvement in electronic healthcare management. It is very much visible since the patients have to avail medical facilities thereby maintaining the rules of social distancing and isolation to break the chain of virus transmission within the society. To achieve this objective, advanced information and communication, technology-based video conferencing tools may be widely used to deliver medical consultancy to the patients in this pandemic situation. Since this entire electronic communication is dependent on the internet, which is itself an open digital space, this electronic communication between the patients and the medical practitioners are highly susceptible to infringement attempt of the adversary. Even the hardware component used by the patients during this electronic healthcare transaction like the camera, speaker, etc. of the end-devices may remain under the control of adversary even after the completion of the electronic transaction. As a result, the adversary may record any personal moment or personal file system of the user without its knowledge. To de-escalate and arrest the access of adversary over the resources of user, it is pertinent to study the risk factors and their security protocols in similar cases to manage the vulnerabilities and to propose the enhanced security model to ensure the integrity of the electronic healthcare transaction. In this paper, authors have studied those existing security protocols to propose a secured audio and video conferencing system through wired and wireless network with control and command of all the resources with the actual user only. The objective of this study is to maintain a logfile in a secure manner to note down the access and release of resources during the audio and video conference.