C Rani

Bio: C Rani is an academic researcher from VIT University. The author has contributed to research in topics: Synchronization & Controller (computing). The author has co-authored 1 publications.

Time compensated models of switching elements for hardware in loop simulation

Abstract: Simulation tools have been extensively used for the design and improvement of electrical systems for decades. The evolution of simulation tools has progressed dramatically in recent years with the advancement in computing technologies. The present trend in simulation is Real Time Simulation where the computer model runs at the same rate as the actual physical time. The only reason to conduct Real-Time Simulation is to connect real hardware to the simulated model. This is where the importance of hardware in the loop simulation emerges where the virtual plant model is controlled using a real controller. Synchronization of external PWM signals with the simulation time step of the virtual plant model is the main concern while conducting HIL simulation of Power Electronic systems. In this work a time compensation algorithm is developed to deduce the accurate switching instant of the control signals. Time compensation hardware is implemented using FPGA and accurate switching, instant is incorporated into the simulation process with the help of time compensated libraries for switching elements. The algorithm is tested by giving PWM signals from external controllers to a virtual buck converter model simulated inside Full Spectrum Simulator (FSS). Results obtained by enabling and disabling the algorithm are analyzed thoroughly and is finding that time compensation greatly helps to obtain maximum accuracy while conducting HIL simulation.

An Event-Driven Real-Time Simulation for Power Electronics Systems Based on Discrete Hybrid Time-Step Algorithm

Abstract: Real-time (RT) hardware-in-the-loop (HIL) simulation aims to speed up the validation process for power electronic systems (PES). The complex PESs with high switching frequency constitute some of the most challenging applications in RT-HIL. Conventional RT-HIL relies on adding extra expensive computing hardware to achieve submicrosecond step size, reducing errors caused by unavoidable sampling delays. This article proposes a CPU-based event-driven RT (EDRT) simulation framework by improving the algorithm rather than using additional hardware. The framework consists of two parts: 1) the synchronous-cycle event detection sampling method, which eliminates the delay error by detecting switching events; and 2) the discrete hybrid time-step numerical algorithm, which combines variable and fixed step-size simulation to improve the calculation efficiency and uses the ideal model to improve the modeling accuracy. The proposed framework is applied to a power electronic transformer with 24 switches and a 20 kHz switching frequency as a simulated case. Comparing the proposed simulation results with experimental results and other simulation results, the proposed EDRT framework can achieve the same numerical accuracy as the offline simulation but only requires 1/36 of the computation time. Furthermore, the hardware cost to achieve the same computational scale is reduced to 1/20 of the conventional HIL.