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C. Roberts

Bio: C. Roberts is an academic researcher from Micron Technology. The author has contributed to research in topics: Universal memory & Reliability (semiconductor). The author has an hindex of 1, co-authored 1 publications receiving 4 citations.

Papers
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Proceedings ArticleDOI
11 Jul 2007
TL;DR: As DRAM and NAND cells are rapidly scaled deep into the nanoscale regime, meeting design and reliability requirements require deeper understanding of single-cell characteristics.
Abstract: As DRAM and NAND cells are rapidly scaled deep into the nanoscale regime, meeting design and reliability requirements require deeper understanding of single-cell characteristics. Some of the challenges are common between these technologies while some are unique. New materials and cell structures are being introduced to address some of these issues and provide further scaling opportunities.

4 citations


Cited by
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Proceedings ArticleDOI
23 Oct 2009
TL;DR: In this paper, a surrogate response surface model (RSM) was developed for peripheral n-type field-effect transistors in a dynamic random-access-memory process flow to identify, model, and analyze process variation.
Abstract: Reduction of electrical parameter variation is essential to achieve high yield and reliability in semiconductor devices. However, variation depends on a large number of process factors, which are often interdependent. In this work, well-calibrated Technology Computer-Aided-Design process and device simulations were performed in a designed experiment to develop an efficient, surrogate response surface model (RSM) of the device parameters as a function of key process factors. Monte Carlo simulations were performed with the RSM to estimate variation and design systems to reduce variation. The approach, illustrated here specifically for peripheral n-type field-effect transistors in a dynamic random-access-memory process flow, is general, easy-to-implement, and a cost-effective way to systematically identify, model, and analyze process variation.

3 citations

Journal ArticleDOI
Goon Ho Park1, Myung-Ho Jung1, Kwan Su Kim1, Hong Bay Chung1, Won-Ju Cho1 
TL;DR: Tunneling barrier engineered charge trap flash (TBE-CTF) memory devices were fabricated using the tunneling barrier engineering technique Variable oxide thickness (VARIOT) barrier and CRESTed barrier consisting of thin SiO 2 and Si 3 N 4 dielectric layers were used as engineered tunneling barriers as discussed by the authors.

3 citations

Proceedings ArticleDOI
02 May 2010
TL;DR: In this paper, the authors present an optimal cell design for the improved reliability characteristics in the level of mass production for the future NAND Flash with floating gate cells, which is a simple way to relieve the short channel effect is increasing the channel boron concentration.
Abstract: One of the critical scaling barriers in sub 30 nm NAND Flash technology node is an abrupt threshold voltage drop of cell transistors by short channel effect. It increases program voltage which leads, in turn, to fatal reliability issues. A simple way to relieve the short channel effect is increasing the channel boron concentration. However it degrades endurance characteristics by deteriorating boosting efficiency on inhibit operation. In this paper, we present an optimal cell design for the improved reliability characteristics in the level of mass production for the future NAND Flash with floating gate cells.

1 citations