C. Toumazou

Bio: C. Toumazou is an academic researcher from Imperial College London. The author has contributed to research in topics: Circuit design & Circuit extraction. The author has an hindex of 2, co-authored 2 publications receiving 106 citations.

Analog IC design automation. I. Automated circuit generation: new concepts and methods

Abstract: The research presented in this paper is concerned with the automation of analog integrated circuit design and, in particular, with a description of methods and techniques employed by the ISAID design system developed at Imperial College, UK. ISAID is comprised of two modules: the circuit generator and the circuit corrector. The circuit generator is based on newly developed methods that are used to handle hierarchical generation of topologies and size MOS transistors so that the performance of designed circuits compare satisfactorily with their specifications. To avoid long design times, simulation is used only after the generation of an initial circuit topology. Simulated performances may therefore be found to differ from the required. One novel feature of the proposed methodology is that in such cases a circuit corrector is invoked to correct the initial design. The circuit corrector is essentially a novel application of qualitative reasoning, which, without iterative simulation analyses performance trade-offs, thereby selects circuit adjustments-transistor size adjustments or topological modifications-that would improve the problematic performances. Several design examples have demonstrated the benefits of the ISAID design approach. >

Analog IC design automation. II. Automated circuit correction by qualitative reasoning

Abstract: For pt. I see ibid., vol. 14, no. 2, p. 218-38 (1995). This part of the paper is focused on a novel application of Qualitative Reasoning, which allows modifications of a circuit's topology to take place in cases where not all performance specifications are met. Within ISAID, this task of post-simulation circuit correction is carried out by the Circuit Corrector. >

Computer-aided design of analog and mixed-signal integrated circuits

Abstract: This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search

Abstract: Analog synthesis tools have traditionally traded quality for speed, substituting simplified circuit evaluation methods for full simulation in order to accelerate the numerical search for solution candidates. As a result, these tools have failed to migrate into mainstream use primarily because of difficulties in reconciling the simplified models required for synthesis with the industrial-strength simulation environments required for validation. We argue that for synthesis to be practical, it is essential to synthesize a circuit using the same simulation environment created to validate the circuit. In this paper, we develop a new numerical search algorithm efficient enough to allow full circuit simulation of each circuit candidate, and robust enough to find good solutions for difficult circuits. The method combines the population-of-solutions ideas from evolutionary algorithms with a novel variant of pattern search, and supports transparent network parallelism. Comparison of several synthesized cell-level circuits against manual industrial designs demonstrates the utility of the approach.

CMOS op-amp sizing using a geometric programming formulation

Abstract: The problem of CMOS op-amp circuit sizing is addressed here. Given a circuit and its performance specifications, the goal is to automatically determine the device sizes in order to meet the given performance specifications while minimizing a cost function, such as a weighted sum of the active area and power dissipation. The approach is based on the observation that the first order behavior of a MOS transistor in the saturation region is such that the cost and the constraint functions for this optimization problem can be modeled as posynomial in the design variables. The problem is then solved efficiently as a convex optimization problem. Second order effects are then handled by formulating the problem as one of solving a sequence of convex programs. Numerical experiments show that the solutions to the sequence of convex programs converge to the same design point for widely varying initial guesses. This strongly suggests that the approach is capable of determining the globally optimal solution to the problem. Accuracy of performance prediction in the sizing program (implemented in MATLAB) is maintained by using a newly proposed MOS transistor model and verified against detailed SPICE simulation.

MAELSTROM: efficient simulation-based synthesis for custom analog cells

Abstract: Analog synthesis tools have failed to migrate into mainstream use primarily because of difficulties in reconciling the simplified models required for synthesis with the industrial-strength simulation environments required for validation. MAELSTROM is a new approach that synthesizes a circuit using the same simulation environment created to validate the circuit. We introduce a novel genetic/annealing optimizer, and leverage network parallelism to achieve efficient simulator-in-the-loop analog synthesis.