C
C. Vasanthanayaki
Researcher at Government College of Engineering, Salem
Publications - 3
Citations - 25
C. Vasanthanayaki is an academic researcher from Government College of Engineering, Salem. The author has contributed to research in topics: Adder & Critical path method. The author has an hindex of 2, co-authored 3 publications receiving 10 citations.
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High performance compact energy efficient error tolerant adders and multipliers for 16-bit image processing applications
TL;DR: To achieve area and energy efficiency, Simplified gate level Approximate Full Adders (SAFAs) are proposed in the inaccurate part of the CEETA and CEETA1 designs and the proposed HPETM1 has a significant amount of power and area savings.
Journal ArticleDOI
High Performance Four Segment Error Tolerant Adder for 8-bit Pixel Depth Image Processing Applications
R. Jothin,C. Vasanthanayaki +1 more
TL;DR: This research proposes a high-performance Carry Select Approximate Full Adder with one error out of the eight possible output cases for high accuracy 8-bit pixel depth image processing applications and offers a savings of 27.82% PDP and 34.39% ADP with respect to the existing ETA-2LOA architecture.
Journal ArticleDOI
Comparison and extension of high performance adders for hybrid and error tolerant applications
TL;DR: In this paper, the authors proposed a 16-bit HPVARA and HPETA-III architectures for hybrid and error tolerant applications, which are used extensively in many computing architectures.