Showing papers by "Chandra Mouli published in 2004"

Isolation techniques for reducing dark current in CMOS image sensors

Abstract: Isolation methods and devices for isolating regions of a semiconductor device. The isolation method and structure include forming an isolating trench in an active area and filling the trench with a doped conductive material containing silicon. Suitable conductive materials containing silicon include polysilicon and silicon-germanium. There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to fill the trench or to partially fill the trench and depositing an insulating material over the epitaxial layer and within the trench to completely fill the trench.

Reduced crosstalk sensor and method of formation

Abstract: Isolation methods and devices for isolating regions of a semiconductor device are disclosed. The isolation methods and structures include forming an isolating trench among pixels or other active areas of a semiconductor device. The trench extends through the substrate to the base layer, wherein a liner may be deposited on the side walls of the trench. A conductive material is deposited into the trench to block electrons from passing through.

CMOS imager technology shrinks and image performance

Abstract: In this paper, we present a performance summary of CMOS imager pixels from 5.2 /spl mu/m to 4.2 /spl mu/m using 0.18 /spl mu/m imager design rules, then to 3.2 /spl mu/m using 0.15 /spl mu/m imager design rules. These pixels support 1.3-megapixel, 2.0-megapixel, and 3.1-megapixel CMOS image sensors for digital still cameral (DSC) applications at 3.3 V, respectively. The 4TC pixels are all based on technology shrinks of Micron's 2P3M imager process, and each of the technology nodes report excellent CMOS imager low-noise, high-sensitivity, low-lag, and low-light performance, matching that of state-of-the-art charged-coupled device (CCD) imagers. We have put a model in place to provide the predictive performance of smaller pixels, and then use that model to discuss performance expectations down to 2.0 /spl mu/m pixels. With the combination of imager design rules, pixel architecture, and process technology tailored for CMOS imagers, we see no fundamental reason that CMOS imagers should not be able to continue matching CCD performance as pixel sizes shrink.

Deuterated structures for image sensors and methods for forming the same

Abstract: A pixel cell with a photo-conversion device and at least one structure includes a deuterated material adjacent the photo-conversion device.

Method and apparatus for reducing effects of dark current and defective pixels in an imaging device

Abstract: A method and apparatus for identifying and compensating for the effects of defective pixels in high resolution digital cameras having image processing apparatus. The apparatus includes a storage system for storing data corresponding to either a dark current reference image and a white reference image and at least one actual image captured by a pixel array, and at least one processor coupled to the storage system for compensating the data corresponding to the actual image based upon the stored data. The method includes capturing and storing both dark and white reference images as well as capturing and storing actual images, identifying pixels that are affected by dark current or are defective pixels, reading data corresponding to pixels of an actual image affected by dark current or that are defective from the storage system and compensating the affected pixels.

Using high-k dielectrics in isolation structures method, pixel and imager device

Abstract: An imager device that has an isolation structure such that pinned photodiode characteristics are maintained without increasing doping levels. The invention provides an isolation structure to maintain pinned photodiode characteristics without increasing doping levels around the photodiode. By creating a substrate region surrounding the charge-collection region of the photodiode, the photodiode may be electrically isolated from the bulk substrate. This region fixes the depletion region so that it does not migrate toward the surface of the substrate or the STI region. By doing so, the region prevents charge from being depleted from the substrate and the accumulation region, reducing dark current.

Methods of forming integrated circuits

Abstract: This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an integrated circuit includes forming a trench isolation mask over a semiconductor substrate. The trench isolation mask defines an active area region and a trench isolation region. An ion implantation is conducted into semiconductive material of the substrate to form a buried region within active area of the substrate. The buried region has a first edge received proximate an edge of the trench isolation region. Using the trench isolation mask, etching is conducted into semiconductive material of the substrate to form an isolation trench. After the ion implantation and after forming the isolation trench, insulative material is formed within the buried region and insulative material is deposited to within the isolation trench. The insulative material received within the isolation trench joins with the insulative material formed within the buried region.

Silicon-based resonant cavity photodiode for image sensors

Abstract: An imager with pixels having a resonant-cavity photodiode. The resonant cavity photodiode increases absorption of light having long wavelengths. A trench is formed for the photodiode and reflective film is grown on the bottom of the trench. The reflective film reflects light that is not initially absorbed back to the active region of the photodiode.

Pixel with strained silicon layer for improving carrier mobility and blue response in imagers

Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.

Transparent conductor based pinned photodiode

Abstract: A pinned photodiode with improved short wavelength light response. In exemplary embodiments of the invention, a gate oxide is formed over a doped, buried region in a semiconductor substrate. A conductor is formed on top of the gate oxide. The gate conductor is transparent, and in one embodiment is a layer of indium-tin oxide. The transparent conductor can be biased to reduce the need for a surface dopant in creating a pinned photodiode region. The biasing of the transparent conductor produces a hole-rich accumulation region near the surface of the substrate. The gate conductor material permits a greater amount of charges from short wavelength light to be captured in the photo-sensing region in the substrate, and thereby increases the quantum efficiency of the photosensor.

Tailoring gate work-function in image sensors

Abstract: Embodiments of the invention provide a method of forming a pixel cell and the resultant pixel cell a photo-conversion device formed at a surface of a substrate and a transistor adjacent to the photo-conversion device. The transistor comprises a gate overlying a channel region. The gate comprises at least one gate region having a work-function greater than a work-function of n+ polysilicon. The channel region comprises respective portions below each gate region. A dopant concentration in at least one portion of the channel region is determined at least in part by the work-function of the respective gate region.

Photonic crystal-based optical elements for integrated circuits and methods therefor

Abstract: Exemplary embodiments of the invention provide photonic crystal-based optical elements for integrated circuits. A photonic crystal optical device comprises a substrate and a plurality of pillars forming a photonic crystal structure over the substrate. The pillars are spaced apart from each other. Each pillar has a height and a horizontal cross-sectional shape. A material with a different dielectric constant than the pillars is provided within the spacing between the pillars. According to exemplary embodiments of the invention, the photonic crystal-based optical element can be an optical interconnect, a lens, or a filter. The photonic crystal-based optical element of the invention can be used to transmit solitons.

Synthesizing semiconductor process flow models

Abstract: Systems and methods of modeling a best-guess semiconductor process flow for fabricating a desired semiconductor device are provided. The best-guess process flow is modeled using an inverse modeling technique. This technique reverse engineers a desired semiconductor device to synthesize a model of a fabrication process that is likely to produce the desired semiconductor device. First, a desired device having one or more desired characteristics is modeled. Then, various process and material parameters, constraints, and actual measured data are used to synthesize one or more unique software models that represent a process flow likely to fabricate the desired device. If more than one process flow is modeled, various parameters are modified iteratively until a unique process flow model is synthesized.

Photon amplification for image sensors

Abstract: A pixel cell having a substrate, photo-conversion device, and at least one dielectric layer over the photo-conversion device. The at least one dielectric layer includes one or more rare earth elements for amplifying the number of photons capable of being converted to charge by the photo-conversion device.

Deep photodiode isolation process

Abstract: A barrier implanted region of a first conductivity type located below an isolation region of a pixel sensor cell and spaced from a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The barrier implanted region is formed by conducting a plurality of deep implants at different energies and doping levels below the isolation region. The deep implants reduce surface leakage and dark current and increase the capacitance of the photodiode by acting as a reflective barrier to electrons generated by light in the doped region of the second conductivity type of the photodiode.

Image sensor with improved dynamic range and method of formation

Abstract: Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor structure comprises at least one semiconductor channel region, at least one gate for controlling the channel region, and first and second leads respectively coupled to a source region on one side of the at least one channel region and a drain region on an opposite side of the at least one channel region. The transistor structure has at least two threshold voltages associated with the at least one channel region, and an I-V characteristic of the transistor structure is determined at least in part by the threshold voltages.

Memory device forming methods

Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.

High density access transistor having increased channel width and methods of fabricating such devices

Abstract: A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to from word lines that intersect the active area lines at the angled segments.

Thermoelectric cooling for imagers

Abstract: An imager is provided with a thermoelectric cooler. The cooler is formed on the back side of the imager to thermoelectrically cool areas of the imager. The cooler removes heat from targeted regions where heat is generated and conducts the heat away from sensitive pixel array regions. Accordingly, dark current is reduced by thermoelectrically cooling the imager.

Transistor structures and transistors with a germanium-containing channel

Abstract: A transistor structure includes a first undoped, silicon-containing channel layer, a buried germanium channel, and a second undoped, silicon-containing channel layer. The first and second channel layers may contain SiGe or, alternatively, Si only. Another transistor structure includes a first channel layer, a buried germanium channel, and a second, undoped channel layer containing silicon and germanium over the buried channel. A further transistor structure includes a first channel layer, a buried germanium channel, and a second channel layer containing compositionally graded SiGe over the buried channel. A still further transistor structure includes a first silicon layer, an undoped or homogeneously doped buried channel containing silicon and germanium, and a second silicon layer over the buried channel.

Semiconductor image sensor comprising a metal mesh filter

Abstract: A semiconductor image sensor utilizing a metal mesh filter to transmit light of a specific wavelength to a photoconversion device, and method of making said image sensor. Semiconductor image sensor pixel cells using varied metal mesh filters may be arranged in a Bayer pattern for color imaging. As a result, the need for using conventional polymer color filters in image sensor applications is eliminated.

Three-Dimensional Characterization and Modeling of Stress Distribution in High-Density DRAM Memory Cells

Abstract: The retention time characteristics in DRAM cells are strongly influenced by various leakage mechanisms near the storage node junction. In this work, we present a full three-dimensional analysis of stress distributions in and around the active area of high-density memory cells. We use a combination of high-resolution metrology analysis and 3D numerical modeling to provide quantitative estimates. Since shallow - trench isolation (STI) process used in high-density cells is one of the major contributors to stress, we study the effects of various materials used to fill the trench. Our electron diffraction contrast (EDC) methodology provides a spatial resolution on the order of 10 nm with sensitivity on of the order of tens of MPa and therefore useful for the analysis of scaled high density memory cells.

Implantation inclinee pour caisson d'isolation

Abstract: L'invention concerne un caisson d'isolation dote d'une region implantee une paroi laterale et dans le fond et situee dans un substrat d'un premier type de conductivite. La region implantee dans une paroi laterale et dans le fond est formee par une implantation inclinee, une implantation de 90°, ou une combinaison d'une implantation inclinee et d'une implantation de 90°, de dopants du premier type de conductivite. La region implantee dans une paroi laterale et dans le fond et situee contre le caisson d'isolation reduit les fuites en surface et le courant d'obscurite.