Showing papers by "Chandra Mouli published in 2005"

Ge diffusion in Ge metal oxide semiconductor with chemical vapor deposition HfO2 dielectric

Abstract: We report a study on Ge diffusion and its impact on the electrical properties of TaN∕HfO2∕Ge metal-oxide-semiconductor (MOS) device. It is found that Ge diffusion depends on the amount of GeO2 formed at the HfO2∕Ge interface and can be retarded by surface nitridation. It is speculated that Ge diffusion is in the form of GeO or Ge-riched HfGeO. Effective suppression of Ge diffusion by NH3 nitridation has resulted in improved electrical properties of TaN∕HfO2∕Ge MOS device, including equivalent oxide thickness (EOT), leakage current, hysteresis, and interface state density. The degradation of leakage current after high temperature post metallization anneal (PMA) is found to be due to Ge diffusion.

Image sensors with optical trench

Abstract: A device and method for providing an optical trench structure for a pixel which guides incoming light onto the photosensor of the pixel. The optical trench structure has an optically reflecting barrier that substantially mitigates optical crosstalk. The optical trench structure is made of low dielectric constant material with an index of refraction that is less than the index of refraction of the material of surrounding layers (e.g., the substrate). This difference in refractive index causes an internal reflection into an optical path existing between a lens and pixel.

Method and apparatus providing an optical guide for an imager pixel having a ring of air-filled spaced slots around a photosensor

Abstract: A device and method to provide an optical guide of a pixel to guide incoming light onto a photosensor of the pixel and to improve the optical crosstalk immunity of an image sensor. The optical guide consists of an optically reflecting barrier formed as a trench that mitigates against optical crosstalk. The optical guide is made of an air-filled ring of spaced slots. In another embodiment, the optical guide structure can be filled with a low dielectric material with an index of refraction that is less than the index of refraction of the material used for the surrounding layers.

Sharing of microlenses among pixels in image sensors

Abstract: A microlens array having microlenses that correspond to more than one color filter and underlying pixel. In one particular embodiment, each microlens is formed to cover one Bayer pattern set, out of a plurality of repeated sets over an entire color filter and pixel array. A semiconductor-based imager includes a pixel array having embedded pixel cells, each with a photosensor, and a microlens array having microlenses that cover more than one embedded pixel cell.

Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation

Abstract: A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface layer has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019 atoms per cm3. The ultra-shallow highly-doped surface layer is formed by diffusion of ions from a doped layer into the substrate or by a plasma doping process. The ultra-shallow pinned layer is in contact with a charge collection region of a second conductivity type.

Recessed Channel Negative Differential Resistance-Based Memory Cell

Abstract: Disclosed herein is an improved recessed thyristor-based memory cell. The disclosed cell comprises in one embodiment a conductive plug recessed into the bulk of the substrate, which is coupled to or comprises the enable gate of the cell. Vertically disposed around this recessed gate is a thyristor, whose anode (source; p-type region) is connected to the bit line and cathode (drain; n-type region) is connected to the word line. Aside from the recessed enable gate, the disclosed cell comprises no other gate, such as an access transistor, and hence is essentially a one-transistor device. As a result, and as facilitated by the vertical disposition of the thyristor, the disclosed cell takes up a small amount of area on an integrated circuit when compared to a traditional DRAM cell. Moreover, the disclosed cell is simple to manufacture in its various embodiments, and is easy to configure into an array of cells. Isolation underneath the cell, while not required in all useful embodiments, assists in improving the data retention of the cell and extends the time needed between cell refresh.

Low dark current image sensors with epitaxial SiC and/or carbonated channels for array transistors

Abstract: A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or carbonated silicon is provided over the substrate of the pixel cell to reduce the dark current leakage.

Semiconductor-on-insulator constructions; and methods of forming semiconductor-on-insulator constructions

Abstract: The invention encompasses a method of forming a semiconductor-on-insulator construction A substrate is provided The substrate includes a semiconductor-containing layer over an insulative mass The insulative mass comprises silicon dioxide A band of material is formed within the insulative mass The material comprises one or more of nitrogen argon, fluorine, bromine, chlorine, iodine and germanium

FinFET device with reduced DIBL

Abstract: FinFET devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and methods for producing the same. The methods involve dopant implants into the insulator layer, thereby creating borophosphosilicate glass (BPSG) diffusion sources within the insulation layer underlying the active regions of the SOI wafer. Backend high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the active regions, thereby forming a retrograde dopant profile extending towards the channel region. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.

Floating-gate structure with dielectric component

Abstract: Floating-gate memory cells having a floating gate with a conductive portion and a dielectric portion facilitate increased levels of charge trapping sites within the floating gate. The conductive portion includes a continuous component providing bulk conductivity to the floating gate. The dielectric portion is discontinuous within the conductive portion and may include islands of dielectric material and/or one or more contiguous layers of dielectric material having discontinuities.

Pixel and imager device having high-k dielectrics in isolation structures

Abstract: An imager device that has an isolation structure such that pinned photodiode characteristics are maintained without increasing doping levels. The invention provides an isolation structure to maintain pinned photodiode characteristics without increasing doping levels around the photodiode. By creating a substrate region surrounding the charge-collection region of the photodiode, the photodiode may be electrically isolated from the bulk substrate. This region fixes the depletion region so that it does not migrate toward the surface of the substrate or the STI region. By doing so, the region prevents charge from being depleted from the substrate and the accumulation region, reducing dark current.

Memory devices, transistors, memory cells, and methods of making same

Abstract: A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel.

Nanotube forming methods

Abstract: A nanotube forming method includes growing a plurality of nanotubes to an intermediate length that is deterministic of nanotube intrinsic conductivity. Individual nanotubes exhibit an effective conductivity, which varies among the plurality of nanotubes. The method includes completing growth of nanotubes exhibiting effective conductivities inside a selected range without completing growth of nanotubes exhibiting effective conductivities outside the selected range. Before completing nanotube growth, the method may further include stopping nanotube growth and screening out nanotubes exhibiting conductivities outside the selected range. The screening out of nanotubes may include deforming or masking nanotubes exhibiting conductivities outside the selected range. Deforming nanotubes may include applying a potential.

Method of forming a memory device having a storage transistor

Abstract: A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line connected to the gate structure. The memory device does not require an additional capacitive storage element.

Non-volatile memory with carbon nanotubes

Abstract: Floating-gate memory cells having carbon nanotubes interposed between the substrate and the tunnel dielectric layer facilitate ballistic injection of charge into the floating gate. The carbon nanotubes may extend across the entire channel region or a portion of the channel region. For some embodiments, the carbon nanotubes may be concentrated near the source/drain regions. For some embodiments, the tunnel dielectric layer may adjoin the substrate in at least a portion of the channel region.

High density memory array having increased channel widths

Abstract: A memory array having decreased cell sizes and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to form word lines that intersect the active area lines at the angled segments.

Method of forming high gain, low noise, photodiode sensor for image sensors

Abstract: Embodiments of the present invention provide a pixel cell for an image sensor that includes a photodiode, which provides high gain, low noise, and low dark current. The pixel cell includes a photodiode comprising layers of a first material and at least a second material in contact with one another. The photodiode generates charge in response to light and also amplifies the charge. The layers may be configured to promote impact ionization by a first carrier type and suppress impact ionization by a second carrier type. The pixel cell also includes a gate of a transistor adjacent to the photodiode and may include readout circuitry for reading out the charge generated and amplified by the photodiode.

Integrated circuit device having non-linear active area pillars

Abstract: An integrated circuit device having non-linear active area pillars. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The pillars are patterned to form non-linear active area lines having angled segments. The conductive layer is patterned to form word lines that intersect the active area lines at the angled segments.

High density memory devices having improved channel widths and cell size

Abstract: A memory device having decreased cell size and having transistors with increased channel widths. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a conductive layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The conductive layer is patterned to from word lines that intersect the active area lines at the angled segments.

Structure for isolating regions, image sensor, and manufacturing method therefor

Abstract: PROBLEM TO BE SOLVED: To provide an isolation method and apparatus for isolating the regions of a semiconductor apparatus SOLUTION: The isolation structure and method include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor The isolation method also includes forming of an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels The isolation method and apparatus further include forming of an isolation trench in an active region and filling the trench with a doped conductive material containing silicon There is also provided a method and structure for isolating the regions by providing a trench in an active area of a substrate, growing an epitaxial layer in the trench to completely fill the trench or to partially fill the trench, and depositing an insulating material over the epitaxial layer and within the trench, to completely fill the trench COPYRIGHT: (C)2006,JPO&NCIPI

Methods of forming integrated circuits, and DRAM circuitry memory cells

Abstract: This invention includes methods of forming integrated circuits, and includes DRAM circuitry memory cells. In one implementation, a method of forming an integrated circuit includes forming a trench isolation mask over a semiconductor substrate. The trench isolation mask defines an active area region and a trench isolation region. An ion implantion is conducted into semiconductive material of the substrate to form a buried region within active area of the substrate. The buried region has a first edge received proximate an edge of the trench isolation region. Using the trench isolation mask, etching is conducted into semiconductive material of the substrate to form an isolation trench. After the ion implantation and after forming the isolation trench, insulative material is formed within the buried region and insulative material is deposited to within the isolation trench. The insulative material received within the isolation trench joins with the insulative material formed within the buried region.

Methods of forming transistor devices associated with semiconductor-on-insulator constructions

Abstract: The invention encompasses a method of forming a semiconductor on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon, fluorine, bromine, chlorine, iodine and germanium.