Showing papers by "Chandra Mouli published in 2007"

Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device

Abstract: A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered doped conductor creates a high dopant concentration in the active area close to the channel region. The rich dopant layer created by the multilayered doped conductor is less susceptible to depletion from trapped charges in the oxide. This improves device reliability at burn-in and lowers junction leakage, thereby providing a longer period between refresh cycles.

Capacitor-less volatile memory cell, device, system and method of making same

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Method and apparatus for providing an integrated circuit having p and n doped gates

Abstract: A method and apparatus providing an integrated circuit having a plurality of gate stack structures having gate oxide layers with differing thicknesses and nitrogen concentrations and gate electrodes with differing conductivity types and active dopant concentrations.

Metal Gate Recessed Access Device (RAD) for DRAM Scaling

Abstract: A functional DRAM with higher data retention characteristics than a planar access device has been demonstrated, using a metal gate recessed access device (RAD). Chemical vapor deposition (CVD) and atomic layer deposition (ALD) were used to deposit titanium nitride (TiN) and tantalum nitride (TaN), respectively. CVD TiN and ALD TaN-CVD TiN laminate gate stacks were integrated with a RAD module. ALD TaN-CVD TiN laminate gates showed enhanced drive current (IDS), higher transconductance (GM), higher mobility (?EFF) and reduced off current (IOFF) characteristics compared to CVD TiN gates. Device characteristics and reliability data for both the planar devices and RADs are presented. The ALD TaN-CVD TiN laminate metal gate RAD showed much improved data retention characteristics compared to a conventional planar device with a poly silicon gate. The optimum thickness of ALD TaN in the laminate stack is discussed.

Semiconductor constructions comprising vertically-stacked memory units that include diodes utilizing at least two different dielectric materials, and electronic systems

Abstract: Some embodiments include vertical stacks of memory units, with individual memory units each having a memory element, a wordline, a bitline and at least one diode. The memory units may correspond to cross-point memory, and the diodes may correspond to band-gap engineered diodes containing two or more dielectric layers sandwiched between metal layers. Tunneling properties of the dielectric materials and carrier injection properties of the metals may be tailored to engineer desired properties into the diodes. The diodes may be placed between the bitlines and the memory elements, or may be placed between the wordlines and memory elements. Some embodiments include methods of forming cross-point memory arrays. The memory arrays may contain vertical stacks of memory unit cells, with individual unit cells containing cross-point memory and at least one diode.

Capacitor-less memory cells and cell arrays

Abstract: A capacitor-less memory cell, memory device, system and process of forming the capacitor-less memory cell includes forming the memory cell in an active area of a substantially physically isolated portion of the bulk semiconductor substrate. A pass transistor is formed on the active area for coupling with a word line. The capacitor-less memory cell further includes a read/write enable transistor vertically configured along at least one vertical side of the active area and operable during a reading of a logic state with the logic state being stored as charge in a floating body area of the active area, causing different determinable threshold voltages for the pass transistor.

Ultrashallow photodiode using indium

Abstract: The invention provides an imager having a p-n-p photodiode with an ultrashallow junction depth. A p+ junction layer of the photodiode is doped with indium to decrease transient enhanced diffusion effects, minimize fixed pattern noise and fill factor loss.

Reduced leakage dram memory cells with vertically oriented nanorods and manufacturing methods thereof

Abstract: Methods and structures are described for reducing leakage currents in semiconductor memory storage cells. Vertically oriented nanorods (403) may be used in the channel region of an access transistor (400). The nanorod diameter can be made small enough to cause an increase in the electronic band gap energy in the channel region of the access transistor, which may serve to limit channel leakage currents in its off -state. In various embodiments, the access transistor may be electrically coupled to a double-sided capacitor (425). Memory devices according to embodiments of the invention, and systems including such devices are also disclosed.

Semiconductor devices and electronic systems comprising floating gate transistors

Abstract: Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

Methods of forming semiconductor constructions, light-conducting conduits, and optical signal progapation assemblies

Abstract: The invention includes optical signal conduits having rare earth elements incorporated therein. The optical signal conduits can, for example, contain rare earth elements incorporated within a dielectric material matrix. For instance, erbium or cerium can be within silicon nanocrystals dispersed throughout dielectric material of optical signal conduits. The dielectric material can define a path for the optical signal, and can be wrapped in a sheath which aids in keeping the optical signal along the path. The sheath can include any suitable barrier material, and can, for example, contain one or more metallic materials. The invention also includes methods of forming optical signal conduits, with some of such methods being methods in which the optical signal conduits are formed to be part of semiconductor constructions.

Stacked non-volatile memory with silicon-carbige-based amorphous-silicon thin-film transistors and manufacturing method thereof

Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors (301) stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer (315) having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack (310) is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate (311) is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer. The thin film transistor can be a FinFET.

Transistor surround gate structure with partial silicon-on-insulator for memory cells, memory arrays, memory devices and systems and methods of forming same

Abstract: A transistor surround gate structure and a method of forming thereof on a semiconductor assembly are described. The transistor surround gate structure is formed on a partial silicon-on- insulator in one direction and on a full silicon-on insulator in a second direction and may be scaled to 4f2 line width for a memory array. A plurality of transistor surround gate structures are utilized as memory storage cells in various memory device applications, such as a dynamic random access memory application, a flash memory application and a single transistor memory cell is utilized in an embedded memory device application, which provide for the use of any one of the memory device applications to be used in a system.