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Showing papers by "Chandra Mouli published in 2012"


Patent
Chandra Mouli1
20 Feb 2012
TL;DR: In this article, the authors present devices and methods for providing JFET transistors with improved operating characteristics, such as a higher diode turn-on voltage and a doped silicon-carbide gate.
Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

5 citations


Patent
Chandra Mouli1
30 Jul 2012
TL;DR: In this paper, the authors present devices and methods for providing JFET transistors with improved operating characteristics, including a PIN gate stack and a higher diode turn-on voltage.
Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

3 citations


Patent
22 Aug 2012
TL;DR: In this article, a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to body, and a dielectric in a portion of the body between the source and drain and a level corresponding to an end of the plurality of APs most adjacent to select gate are described and claimed.
Abstract: Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

1 citations


Patent
Chandra Mouli1
12 Sep 2012
TL;DR: A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel, which prevents the leakage of stored charge from the transistor channel into a bulk substrate as discussed by the authors, and methods for fabricating semiconductor devices that include energy barriers are also disclosed.
Abstract: A semiconductor device structure includes a transistor with an energy barrier beneath its transistor channel. The energy barrier prevents leakage of stored charge from the transistor channel into a bulk substrate. Methods for fabricating semiconductor devices that include energy barriers are also disclosed.

1 citations


Patent
Chandra Mouli1
17 Dec 2012
TL;DR: In this paper, the authors describe memory cells that contain floating bodies and gated diodes, where the floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure.
Abstract: Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells.

Patent
Chandra Mouli1
14 Feb 2012
TL;DR: In this paper, the authors describe memory cells that contain floating bodies and gated diodes, where the floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure.
Abstract: Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells.