Showing papers by "Chandra Mouli published in 2018"

A Self-Consistent, Semiclassical Electrothermal Modeling Framework for Mott Devices

Abstract: Mott materials have been investigated since late 1950s for their remarkably abrupt insulator to metal transition (IMT) in response to changes in temperature, strain, or electrical stimulus. Interest in these materials has been revived by recent demonstration of nanosecond-scale switching along with reproducible and fully reversible transitions in VO2-based thin film devices. These phenomena make VO2-based Mott insulator devices technologically relevant for various applications, such as memory selectors, logic switches, and building blocks for neuromorphic computing. Several groups have provisionally attributed the IMT switching to Joule heating. However, an electrothermal device simulation framework that self-consistently reproduces IMT phase transition, and in addition, explaining a variety of electrical/optical phenomena associated with IMT is still lacking. In this paper, we develop a self-consistent electrothermal device simulation framework which captures these key experimental attributes of IMT using VO2 as a model material. This framework will enable predictive modeling as well as provide insight on switching mechanisms and design of novel Mott insulator devices.

Non-poissonian behavior of hot carrier degradation induced variability in MOSFETs

Abstract: This paper reports new experimental findings about the variability of the MOSFET threshold voltage (V T ) introduced by hot carrier (HC) degradation. Previously, it was reported that the V t shift due to HC stress (ΔV t ) follows a Poissonian behavior, i.e. the standard deviation of ΔV t distribution is proportional to the square root of its mean value. Here, we show data coming from very different devices over a wide range of stress levels that deviates from the poissonian behavior under two particular conditions. First, in the initial stage of the HC stress ΔV t may exhibit a super-poissonian behavior, i.e. its standard deviation is related to the mean value yet by a power law but with an exponent larger than 0.5, that will then tend to the square root dependence as the stress continues. Second, and most notably, for very high stress levels ΔV t standard deviation tends to saturate to a maximum value, or even decrease in some cases, although HC degradation keeps increasing. A new physical model able to explain these phenomena is proposed and validated with numerical simulations. Quantitative agreement of statistical simulation with experimental data, hence predictive capability of the model, could be attained only by considering a realistic 3D geometry and the atomistic nature of both channel doping and HC induced trapped charge.

Emerging Memory Modeling Challenges (Invited Paper)

Abstract: Emerging Memory (EM) is a broad class of memory devices leveraging a wide spectrum of physical phenomena and/or material properties, that go beyond the charge storage concept of more conventional NAND and DRAM technologies. Availability of physical models and simulation tools to understand their behavior, predict performance, engineer materials and cell architecture would be extremely useful for their successful development. However, such tools are not always available because of the diversity and complexity of the physical mechanisms. This paper would like to review the main trends of the on-going modeling and simulation activities in the field of EM, trying to point out what are the needs and challenges for the future.

Methods of forming integrated structures comprising vertical channel material and having conductively-doped semiconductor material directly against lower sidewalls of the channel material

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

저 커패시턴스 기판 관통 비아 구조물

Abstract: 본 발명에 따른 장치 및 방법은 저 커패시턴스 기판 관통 비아 구조물의 형성을 위해 개시된다. 예시적인 장치는 기판에 형성된 개구를 포함하되, 개구는 하나의 측벽, 개구의 측벽 상에 적어도 형성된 제1 유전체, 제1 유전체 상에 적어도 형성된 제1 전도체, 제1 전도체 상에 적어도 형성된 제2 유전체, 및 제2 유전체의 측벽 상에 적어도 형성된 제2 전도체를 가진다.