Chang-Hoon Choi

Bio: Chang-Hoon Choi is an academic researcher from Samsung. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 15, co-authored 72 publications receiving 878 citations. Previous affiliations of Chang-Hoon Choi include Stanford University.

Impact of gate direct tunneling current on circuit performance: a simulation study

Abstract: The influence of gate direct tunneling current on ultrathin gate oxide MOS (1.1 nm/spl les/t/sub ox/spl les//1.5 nm, L/sub g/=50-70 nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low V/sub dd/ static-logic circuits. However, dynamic logic and analog circuits are more significantly influenced by the off-state leakage current for oxide thickness below 1.5 nm, under low-voltage operation. Based on the study, the oxide thicknesses which ensure the International Technological Roadmap for Semiconductors (ITRS) gate leakage limit are outlined both for high-performance and low-power devices.

An accurate and efficient high frequency noise simulation technique for deep submicron MOSFETs

Abstract: Based on an active transmission line concept and two-dimensional (2-D) device simulations, an accurate and computationally efficient simulation technique for high frequency noise performance of MOSFETs is demonstrated. Using a Langevin stochastic source term model and small-signal equivalent circuit of the MOSFET, three intrinsic noise parameters (/spl gamma/, /spl delta/, and c) for the drain noise and induced gate noise are calculated. Validity and error analysis for the simulation are discussed by comparing the simulation results with theoretical results as well as measured data.

MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)

Abstract: An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green's function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance.

Direct tunneling current model for circuit simulation

Abstract: This paper presents a compact direct tunneling current model for circuit simulation to predict ultra-thin gate oxide (<2.0 nm) CMOS circuit performance by introducing an explicit surface potential model with quantum-mechanical corrections. It demonstrates good agreement with the results from the numerical solver and measured data for the very-thin gate oxide thicknesses ranging 1.3-1.8 nm.

Optical measuring apparatuses

Abstract: An optical measuring apparatus may include a light source, linear polarizer, polarized beam splitter, quarter wave plate, objective lens, and/or light receiver. The polarized beam splitter may be configured to transmit linearly polarized light from the linear polarizer to any one of a first and second optical path. The quarter wave plate may be configured to circularly polarize light transmitted through the first optical path from the polarized beam splitter and transmit the circularly polarized light to an object to be measured, and the quarter wave plate may be configured to linearly polarize the circularly polarized light reflected from the object to be measured and transmit the linearly polarized reflected light to the second optical path of the polarized beam splitter. The objective lens may be configured to generate light having different wavelengths by generating chromatic aberration in the circularly polarized light from the quarter wave plate.

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Abstract: The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Noise modeling for RF CMOS circuit simulation

Abstract: The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation

Abstract: This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context

Imaging terminal having focus control

Abstract: There is set forth herein an imaging terminal having an image sensor array and a variable lens assembly for focusing an image onto the image sensor array. In one embodiment, an imaging terminal can include one or more focusing configuration selected from the group comprising a full set focusing configuration, a truncated set focusing configuration and a fixed focusing configuration. When a full set focusing configuration is active, a full set of candidate focus settings can be active when the imaging terminal determines a focus setting of the terminal responsively to a trigger signal activation. When a truncated set focusing configuration is active, a truncated range of candidate focus settings can be active when the imaging terminal determines a focus setting of the terminal responsively to a trigger signal activation. When a fixed focusing configuration is active, the focus setting of the imaging lens assembly can be fixed so that a predetermined lens assembly focus setting is active when a trigger signal is active.