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Chang-Lee Chen

Bio: Chang-Lee Chen is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Circuit design & Integrated circuit. The author has an hindex of 3, co-authored 6 publications receiving 307 citations.

Papers
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Journal ArticleDOI
TL;DR: In this paper, the authors describe the rationale and development of a wafer-scale three-dimensional (3D) integrated circuit technology and the essential elements of the 3D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision waferwafer alignment using an in-house developed alignment system, low-temperature wafer wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances.
Abstract: The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described

292 citations

Journal ArticleDOI
TL;DR: In this paper, the authors studied gate-breakdown mechanisms in GaAs MESFETs by numerical simulation and found that the breakdown voltage is highest for the overlapping-gate MES-FET with LTG GaAs passivation, which agrees with the experimental results reported previously.
Abstract: Gate-breakdown mechanisms in GaAs MESFETs have been studied by numerical simulation. The devices simulated include normal passivated and unpassivated MESFETs as well as overlapping-gate MESFETs passivated with low-temperature-grown (LTG) GaAs, normal GaAs, and silicon dioxide. The breakdown voltage is the highest for the overlapping-gate MESFET with LTG GaAs passivation, which agrees with the experimental results reported previously. The high breakdown voltage is the result of an altered electric field near the drain-edge of the Schottky-contact gate. This field modification is achieved most effectively by using an overlapping gate structure. The LTG GaAs is the best passivation layer because of its high resistivity and breakdown-field strength.

17 citations

Journal ArticleDOI
TL;DR: In this article, a physical thermal model is parameterized to provide better prediction of circuit performance in 3D-SOI technologies, and the model is applicable for different circuits designed in the 3-dimensional-soI technology.
Abstract: Thermal test structures and ring oscillators (ROs) are fabricated in 0.18-mum three-dimensional (3-D)-SOI technology. Measurements and electrothermal simulations show that thermal and parasitic effects due to 3-D packaging have a significant impact on circuit performance. A physical thermal model is parameterized to provide better prediction of circuit performance in 3-D technologies. Electrothermal simulations using the thermal model show good agreement with measurement data; the model is applicable for different circuits designed in the 3-D-SOI technology. By studying the phase noise of ROs, the device noise properties of 3-D-SOI technology are also characterized and compared with conventional bulk CMOS technology.

4 citations

Proceedings ArticleDOI
01 Oct 2013
TL;DR: A collection of slides covering the following topics: bonding, 3D integrated circuit process flow, lithographic requirements, 3-tier single-photon laser-radar focal plane, Nyquist-limited IR focal planes, CMOS technology and SWIR detectors is presented in this paper.
Abstract: Presents a collection of slides covering the following topics: bonding; 3D integrated circuit process flow; lithographic requirements; 3-tier single-photon laser-radar focal plane; Nyquist-limited IR focal planes; CMOS technology and SWIR detectors.

2 citations


Cited by
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Journal ArticleDOI
22 Dec 2009
TL;DR: An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules and the proposed TSV check and repair scheme can increase the assembly yield up to 98%.
Abstract: An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the I/O speed to > 1600 Mb/s for 4 rank/module and 2 module/channel case since the master isolates all chip I/O loadings from the channel. Statistical analysis shows that the proposed TSV check and repair scheme can increase the assembly yield up to 98%. By providing extra VDD/VSS edge pads, power noise is reduced to < 100 mV even if all 4 ranks are refreshed every clock cycle consecutively.

557 citations

Journal ArticleDOI
27 Feb 2009
TL;DR: The challenges associated with the 3D hyperintegration technologies are addressed, including integration architectures and design tools, yield and cost, thermal and mechanical constraints, and manufacturing infrastructure as discussed by the authors.
Abstract: Three-dimensional (3-D) hyperintegration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components to form highly integrated micro-nano systems. This 3-D hyperintegration is expected to lead to an industry paradigm shift due to its tremendous benefits. Worldwide academic and industrial research activities currently focus on technology innovations, simulation and design, and product prototypes. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of InfoTech-NanoTech-BioTech systems. This paper overviews the 3-D hyperintegration and packaging technologies, including motivations, key technology platforms, status, and perspectives towards commercialization. The challenges associated with the 3-D technologies are addressed, including integration architectures and design tools, yield and cost, thermal and mechanical constraints, and manufacturing infrastructure.

346 citations

Journal ArticleDOI
TL;DR: In this paper, a GaN high electron mobility transistors (HEMTs) were fabricated using an overlapping-gate technique in which the drain-side edge of the metal gate overlaps on a high breakdown and high dielectric constant dielectrics.
Abstract: GaN high electron mobility transistors (HEMTs) were fabricated using an overlapping-gate technique in which the drain-side edge of the metal gate overlaps on a high breakdown and high dielectric constant dielectric. The overlapping structure reduces the electric field at the drain-side gate edge, thus increasing the breakdown of the device. A record-high three-terminal breakdown figure of 570 V was achieved on a HEMT with a gate-drain spacing of 13 /spl mu/m. The source-drain saturation current was 500 mA/mm and the extrinsic transconductance 150 mS/mm.

344 citations

Journal ArticleDOI
18 Oct 2010
TL;DR: Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3- D SoCs at low area and power and digital gates can directly drive signals through TSVs at high speed and low power.
Abstract: In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

324 citations

Journal ArticleDOI
TL;DR: Testing challenges for 3D ICs are described, including problems that are unique to 3D integration, and early research results in this area are summarized.
Abstract: One of the challenges for 3D technology adoption is the insufficient understanding of 3D testing issues and the lack of DFT solutions. This article describes testing challenges for 3D ICs, including problems that are unique to 3D integration, and summarizes early research results in this area. Researchers are investigating various 3D IC manufacturing processes that are particularly relevant to testing and DFT. In terms of the process and the level of assembly that 3D ICs require, we can broadly classify the techniques as monolithic or as die stacking.

322 citations