This paper compares circular gate (CG) tunnel field effect transistor (TFET) and uniform gate Heterojunction (HJ) TFET as label-free biosensors based on dielectric modulation. Neutral and charged biomolecules with different values of dielectric constant are considered. Sensitivities of partially filled nanogaps arising out of steric hindrance in both the biosensors for concave, convex, increasing and decreasing step profiles of biomolecules are compared. The effect of probe position on sensitivities of the two biosensors is reported for various cases. A status map is presented, plotting the sensitivities of some of the most significant works in applications of FET as label-free biosensors along with sensitivities of the proposed devices. CG TFET exhibits higher sensitivity than HJ TFET due to its non-uniform gate architecture. The sensitivities of the TFETs are highly dependent on the position of biomolecules (steric hindrance and probe position) with respect to the tunnel junction. A maximum sensitivity of $1.31\times 10^{8}$ ( $3.382\times 10^{6}$ ) is achieved for fully filled nanogap in CG TFET (HJ TFET) for dielectric constant 12.

Comparative Analyses of Circular Gate TFET and Heterojunction TFET for Dielectric-Modulated Label-Free Biosensing

This letter reports for the first time a full experimental study of performance boosting of tunnel FETs (TFETs) and MOSFETs by negative capacitance (NC) effect. We discuss the importance of capacitance matching between a ferroelectric NC and a device capacitance to achieve hysteretic and non-hysteretic characteristics. PZT ferroelectric capacitors are connected to the gate of three terminals TFETs and MOSFETs and partial or full matching NC conditions for amplification and stability are obtained. First, we demonstrate the characteristics of hysteretic and non-hysteretic NC-TFETs. The main performance boosting is obtained for the non-hysteretic NC-TFET, where the ON-current is increased by a factor of 500 times, transconductance is enhanced by three orders of magnitude, and the low slope region is extended. The boosting of performance is moderate in the hysteretic NC-TFET. Second, we investigate the impact of the same NC booster on MOSFETs. Subthreshold swing as steep as 4 mV/decade with a 1.5-V hysteresis is obtained on a commercial device fabricated in 28-nm CMOS technology. Moreover, we demonstrate a non-hysteretic NC-MOSFET with a full matching of capacitances and a reduced subthreshold swing down to 20 mV/decade.

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Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects.

In this paper, a new 2-D analytical model for the surface potential of a dual-metal-gate double-gate tunnel field-effect transistor is presented. It takes into account the effects of the drain and gate voltages, gate metal work function, insulator thickness, silicon film thickness, and source and drain depletions. The surface potential thus obtained is used to calculate the tunneling widths at both the source and drain junctions, which are subsequently used as the limits for the integration of the band-to-band generation rate in order to arrive at the tunneling current. In this paper, the band-to-band tunneling is considered to take place through both the source as well as the drain depletion regions. Our model accounts for the variable drain doping through a fitting function, which is postulated based on the theory of generation current, and the results have been found to predict the correct ambipolar behavior of the tunneling field-effect transistors. The results of our model, both for the surface potential and the tunneling current, match very well with those obtained through the TCAD simulations.

Analytical Surface Potential and Drain Current Models of Dual-Metal-Gate Double-Gate Tunnel-FETs

The implementation and operation of the nonvolatile ferroelectric memory (NVM) tunnel field effect transistors with silicon-doped HfO2 is proposed and theoretically examined for the first time, showing that ferroelectric nonvolatile tunnel field effect transistor (Fe-TFET) can operate as ultra-low power nonvolatile memory even in aggressively scaled dimensions. A Fe-TFET analytical model is derived by combining the pseudo 2-D Poisson equation and Maxwell’s equation. The model describes the Fe-TFET behavior when a time-dependent voltage is applied to the device with hysteretic output characteristic due to the ferroelectric’s dipole switching. The theoretical results provide unique insights into how device geometry and ferroelectric properties affect the Fe-TFET transfer characteristic. The recently explored ferroelectric, silicon-doped HfO2 is employed as the gate ferroelectric. With the ability to engineer ferroelectricity in HfO2 thin films, a high-K dielectric well established in memory devices, the silicon-doped HfO2 opens a new route for improved manufacturability and scalability of future 1-T ferroelectric memories. In the current research, a Si:HfO2 based Fe-TFET with large memory window and low power dissipation is designed and simulated. Utilizing our presented model, the device characteristics of a Fe-TFET that takes full benefits from Si:HfO2 is compared with the same devices using well-known perovskite ferroelectrics. Finally, the Fe-TFET is compared with a conventional ferroelectric memory transistor highlighting the advantages of using tunneling memory devices.

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Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric

In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified. The dual-modulation effects in TFETs that the surface potential of the channel is alternatively controlled by the gate bias and drain bias in different operating regimes are emphasized and studied. The transition point corresponding to the switching between the two operating regimes is also analyzed quantitatively. For the first time, a closed-form analytical model of the surface potential in TFETs, including the impacts of both the gate voltage and drain voltage is proposed. Furthermore, a compact current model of the TFET-based on the derived surface potential expression is given. The model predicted tunneling current agree well with the TCAD simulation results in all operating regions of TFETs, which will be helpful for the circuit properties simulation of the TFET.

An Analytical Surface Potential Model Accounting for the Dual-Modulation Effects in Tunnel FETs

In this paper, a closed-form current model for bulk tunneling field-effect transistor (TFET) is put forward. Based on the operation mechanism, the channel surface potential ϕ
 sf which involves the impact of both the gate and the drain voltages is established for the first time. In addition, a new calculation method for the dynamic tunneling width, which is the critical parameter for the TFET modeling, is derived from the surface potential. The surface-potential-based current model is established which is in a good agreement with TCAD simulation results.

Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling

The low frequency noise (LFN) mechanisms of TFETs with different source junction design are experimentally studied for the first time, including the random telegraph signal (RTS) noise. Different from MOSFET, due to the non-local band-to-band tunneling (BTBT) mechanism and small LFN-generating area, both 1/f and 1/f 2 LFN dependence can be observed in large TFETs with large device to device variability, as well as high noise. It is found that the “active” traps responsible for the noise mechanism are located in the area where electron-hole pairs generated by non-local BTBT, and the trap located at the maximum junction electric field tends to have relatively weak impacts on the TFET noise. With new abrupt tunnel junction design, it is observed that the device variability can be effectively alleviated with much lower noise level. In addition, a single-trap-induced RTS noise in TFETs with different source junction design is also experimentally investigated. New features, including strong V D dependence of RTS parameters and significantly high amplitude (~28%), indicate the desirable requirement for the source junction optimization in TFETs.

Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering

The invention relates to a short gate tunneling field effect transistor of a vertical non-uniform doping channel and a preparation method thereof. The short gate tunneling field effect transistor is provided with a vertical channel, the doping in a channel area is slowly varying non-uniform doping, the doping densities of the channel are in Gaussian distribution along the vertical direction, the doping density of the channel in the position close to a drain terminal is higher, and the doping density of the channel in the position close to a source terminal is lower; and in addition, two sides of the vertical channel are provided with dual control gates, each control gate is in an L-shaped short gate structure, and the channel is provided with an area which is not covered with a gate in the position close to the drain terminal, and is provided with an area which is over-covered with a gate in a source area. Compared with the existing TFET (Tunneling Field Effect Transistor), the short gate tunneling field effect transistor disclosed by the invention effectively suppresses the influence of a drain terminal electric field on the tunneling width in the source terminal tunneling junction, weakens the super e exponential relationship of output tunneling current on drain terminal voltage, and obviously improves the output characteristics of a device. Simultaneously, the tunneling field effect transistor is also conductive to the increase of device conducting current, and a sheerer subthreshold gradient is obtained.

Short-gate tunnelling field-effect transistor of vertical non-uniform doped channel and preparation method therefor

In this paper, a closed-form physical capacitance model for bulk tunnel FETs (TFETs) is proposed based on the surface potential approach for the first time. Fundamentally different from that in the MOSFET, the channel surface potential φsf in the TFET is alternately controlled by the drain bias and gate bias in different operation regions. On the basis of physical insight into the operation mechanism, the analytical model of φsf as a function of terminal bias is established. The Gaussian box is introduced to predict the surface potential profile near the source-body junction. Furthermore, the surface-potential-based capacitance model is derived and the calculated terminal capacitances show good agreement with the TCAD simulation results. With the essential physics considered, excellent validity of the model is achieved for bulk TFETs with a large range of structure parameters and SOI/double-gate (DG) TFETs.

Chao Wang

Papers

An Analytical Surface Potential Model Accounting for the Dual-Modulation Effects in Tunnel FETs

Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling

Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering

Short-gate tunnelling field-effect transistor of vertical non-uniform doped channel and preparation method therefor

A closed-form capacitance model for tunnel FETs with explicit surface potential solutions