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Showing papers by "Charles E. Leiserson published in 1987"


Proceedings Article
01 Dec 1987

51 citations


Proceedings ArticleDOI
12 Oct 1987
TL;DR: In this paper, the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations was explored, and it was shown that the number of pins per chip can often be reduced by connecting chips with shared bus interconnections.
Abstract: This paper explores the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations. By connecting chips with shared bus interconnections, as opposed to point-to-point interconnections, we show that the number of pins per chip can often be reduced. For example, for infinitely many n, we exhibit permutation architectures with ⌈√n⌉ pins per chip that can realize any of the n cyclic shifts on n chips in one clock tick. When the set of permutations forms a group with p elements, any permutation in the group can be realized in one clock tick by an architecture with O(√p lg p) pins per chip. When the permutation group is abelian, O(√p) pins suffice. These results are all derived from a mathematical characterization of uniform permutation architectures based on the combinatorial notion of a difference cover.

15 citations


01 Feb 1987
TL;DR: An algorithm is presented for determining the connectivity of a set of N rectangles in the plane, a problem central to avoiding aliasing in VLSI design rule checkers, and runs in O(N 1g N) time and requires no more than O( N) transfers between primary and secondary memory.
Abstract: : An algorithm is presented for determining the connectivity of a set of N rectangles in the plane, a problem central to avoiding aliasing in VLSI design rule checkers. Previous algorithms for this problem either worked slowly with a small amount of primary memory space, or worked quickly but used more space. Our algorithm uses O(W) primary memory space, where W, the scan width, is the maximum number of rectangles to cross any vertical cut. The algorithm runs in O(N 1g N) time and requires no more than O(N) transfers between primary and secondary memory. Keywords: Very large scale integration; Computational geometry; Design rule checking; Algorithms; Rectangles; Connected components; Scanning.

3 citations


Proceedings Article
01 Jan 1987
TL;DR: This paper explores the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations by connecting chips with shared bus interconnections, as opposed to point-to-point interConnections, and shows that the number of pins per chip can often be reduced.