Showing papers by "Charles E. Leiserson published in 1990"

Introduction to Algorithms

Abstract: From the Publisher: The updated new edition of the classic Introduction to Algorithms is intended primarily for use in undergraduate or graduate courses in algorithms or data structures. Like the first edition,this text can also be used for self-study by technical professionals since it discusses engineering issues in algorithm design as well as the mathematical aspects. In its new edition,Introduction to Algorithms continues to provide a comprehensive introduction to the modern study of algorithms. The revision has been updated to reflect changes in the years since the book's original publication. New chapters on the role of algorithms in computing and on probabilistic analysis and randomized algorithms have been included. Sections throughout the book have been rewritten for increased clarity,and material has been added wherever a fuller explanation has seemed useful or new information warrants expanded coverage. As in the classic first edition,this new edition of Introduction to Algorithms presents a rich variety of algorithms and covers them in considerable depth while making their design and analysis accessible to all levels of readers. Further,the algorithms are presented in pseudocode to make the book easily accessible to students from all programming language backgrounds. Each chapter presents an algorithm,a design technique,an application area,or a related topic. The chapters are not dependent on one another,so the instructor can organize his or her use of the book in the way that best suits the course's needs. Additionally,the new edition offers a 25% increase over the first edition in the number of problems,giving the book 155 problems and over 900 exercises thatreinforcethe concepts the students are learning.

A timing analysis of level-clocked circuitry

Abstract: This paper presents an algorithm for verifying proper timing in VLSI circuits where latches are controlled by the levels (high or low) of the controlling clocks rather than the transitions (edges) of the clocks. Such level-clocked circuits are frequently used in MOS VLSI design. A level-clocked circuit is modeled as a graph G = (V, E), where V consists of components -- latches and functional elements --and E represents intercomponent connections. The algorithm verifies the proper timing of a circuit in worst-case O (|V ||E |) time and O (|V | + |E |) space. Our analysis decouples the problem of generating timing constraints from the problem of efficiently checking them. We show how various "base step" functions can be used to provide sufficient conditions for a circuit to operate properly, and we provide a new base step function which is less pessimistic than those used in previous timing verifiers, yet correctly handles timing constraints that are "cyclic" or extend across the boundaries of multiple clock phases or cycles. The base step function is used to derive a "computational expansion" of the circuit from which a collection of simple linear constraints are derived. These constraints can be efficiently checked using standard graph algorithms.

The organization of permutation architectures with bused interconnections

Abstract: The problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations is explored. By connecting chips with shared bus interconnections, as opposed to point-to-point interconnections, it is shown that the number of pins per chip can often be reduced. As an example, for infinitely many n, the authors exhibit permutation architectures that can realize any of the n cyclic shifts on n chips in one clock tick, where the upper limit on the number of pins per chip is the greatest integer >

Organization of systems with bussed interconnections

Abstract: This thesis investigates several aspects of the organization of digital systems that employ bussed interconnections. The thesis focuses on two application domains for busses: communication architectures and control mechanisms, and explores the capabilities of busses as interconnection media, computation devices, and transmission channels. We investigate the organization of permutation architectures that employ bussed interconnections. We explore the problem of efficiently permuting data stored in VLSI chips in accordance with a predetermined set of permutations. By connection chips with shared bus interconnections, as opposed to point-to-point interconnections, we show that the number of pins per chip can often be reduced. We also consider uniform permutation architectures that realize permutations in several clock ticks, instead of one, and show that further savings in the number of pins per chip can be obtained. Exploring efficient utilization of busses for implementing arbitration mechanisms, we investigate priority arbitration schemes that use busses to arbitrate among n modules in a digital system. We focus on distributed mechanisms that employ m busses, for lg n $\leq$ m $\leq$ n, and use asynchronous combinational arbitration logic. A widely used distributed asynchronous mechanism is the binary arbitration scheme, which with m = lg n busses arbitrates in t = lg n units of bus-settling time. We present a new asynchronous scheme--binomial arbitration--that by using m = lg n + 1 busses reduces the arbitration time to t = ${1\over2}$ lg n. Extending this result, we present the generalized binomial arbitration scheme that achieves a bus-time tradeoff of the form m = $O(tn\sp{1/t})$ between the number of arbitration busses m, and the arbitration time t (in units of bus-settling time), for values of 1 $\leq$ t $\leq$ lg n and lg n $\leq$ m $\leq$ n. Our schemes are based on a novel analysis of data-pendent delays, and can be adopted with no changes to existing hardware and protocols; they merely involve selecting a good set of priority arbitration codewords. The digital transmission line bus model presented accounts for the propagation time of signals along bus lines and assumes that the propagating signals are always valid digital signals. A widely held misconception is that in the digital transmission line model the arbitration time of the binary arbitration scheme is at most 4 units of bus-propagation delay. We formally disprove this conjecture by demonstrating that the arbitration time of the binary arbitration scheme is heavily dependent on the arrangement of the arbitrating modules in the system. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.) (Abstract shortened with permission of school.)