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Charles E. Leiserson

Researcher at Massachusetts Institute of Technology

Publications -  190
Citations -  50798

Charles E. Leiserson is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Cilk & Scheduling (computing). The author has an hindex of 65, co-authored 185 publications receiving 49312 citations. Previous affiliations of Charles E. Leiserson include Vassar College & Carnegie Mellon University.

Papers
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Journal ArticleDOI

Provably Efficient Online Nonclairvoyant Adaptive Scheduling

TL;DR: G-RAD and S-R AD are the first non-clairvoyant scheduling algorithms that guarantee provable efficiency, fairness and minimal overhead, and are described as O(1)-competitive for arbitrary batched jobs.
Proceedings ArticleDOI

The Cilkprof Scalability Profiler

TL;DR: Cilkprof as mentioned in this paper is a scalability profiler for multithreaded Cilk computations that collects work (serial running time) and span (critical-path length) data for each call site in the computation to assess how much each call sites contributes to the overall work and span.
Proceedings ArticleDOI

Deriving divide-and-conquer dynamic programming algorithms using solver-aided transformations

TL;DR: A framework allowing domain experts to manipulate computational terms in the interest of deriving better, more efficient implementations of dynamic programming algorithms that have better locality and are significantly more efficient than traditional loop-based implementations is introduced.

Retiming synchronous circuitry

Abstract: This paper describes a circuit transformation calledretiming in which registers are added at some points in a circuit and removed from others in such a way that the functional behavior of the circuit as a whole is preserved. We show that retiming can be used to transform a given synchronous circuit into a more efficient circuit under a variety of different cost criteria. We model a circuit as a graph in which the vertex setV is a collection of combinational logic elements and the edge setE is the set of interconnections, each of which may pass through zero or more registers. We give anO(?VźE?lg?V?) algorithm for determining an equivalent retimed circuit with the smallest possible clock period. We show that the problem of determining an equivalent retimed circuit with minimum state (total number of registers) is polynomial-time solvable. This result yields a polynomial-time optimal solution to the problem of pipelining combinational circuitry with minimum register cost. We also give a chacterization of optimal retiming based on an efficiently solvable mixed-integer linear-programming problem.
Patent

Parallel computer system with physically separate tree networks for data and control messages

TL;DR: In this paper, a digital computer comprises a plurality of processing elements, a communications router, and a control network, each processing element performs data processing operations in connection with commands, at least some of the processing elements performing the data processing operation in relation with the commands in messages they receive over the control network.