Charles E. Leiserson

Bio: Charles E. Leiserson is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Cilk & Scheduling (computing). The author has an hindex of 65, co-authored 185 publications receiving 49312 citations. Previous affiliations of Charles E. Leiserson include Vassar College & Carnegie Mellon University.

Optimizing synchronous systems

Abstract: The complexity of integrated-circuit chips produced today makes it feasible to build inexpensive, special-purpose subsystems that rapidly solve sophisticated problems on behalf of a general-purpose host computer. This paper contributes to the design methodology of efficient VLSI algorithms. We present a transformation that converts synchronous systems into more time-efficient, systolic implementations by removing combinational rippling. The problem of determining the optimized system can be reduced to the graph-theoretic single-destination-shortest-paths problem. More importantly from an engineering standpoint, however, the kinds of rippling that can be removed from a circuit at essentially no cost can be easily characterized. For example, if the only global communication in a system is broadcasting from the host computer, the broadcast can always be replaced by local communication.

Content delivery network service provider (CDNSP)-managed content delivery network (CDN) for network service provider (NSP)

Abstract: A CDN service provider shares its CDN infrastructure with a network to enable a network service provider (NSP) to offer a private-labeled network content delivery network (NCDN or “private CDN”) to participating content providers. The CDNSP preferably provides the hardware, software and services required to build, deploy, operate and manage the CDN for the NCDN customer. Thus, the NCDN customer has access to and can make available to participating content providers one or more of the content delivery services (e.g., HTTP delivery, streaming media delivery, application delivery, and the like) available from the global CDN without having to provide the large capital investment, R&D expense and labor necessary to successfully deploy and operate the network itself. Rather, the global CDN service provider simply operates the private CDN for the network as a managed service.

Area-Efficient VLSI Computation

Abstract: The remarkable advance of very large scale integrated (VLSI) circuitry has sparked research into the design of algorithms suitable for direct hardware implementation. To exploit the massive parallelism offered by two-dimensional VLSI circuit technologies, the physical and logical structures of algorithms must be harmonized. A major goal is to design algorithms that are area-efficient as well as time-efficient, using complexity measures that reflect the true implementation costs. The two parts of this thesis address these two types of efficiency from a unified viewpoint of mathematics and engineering. Systolic systems make for high-performance hardware designs by marrying the ideas of pipelining and multiprocessing. A systolic system is a network of small, rhythmically computing processors which perform a service on behalf of a host computer. Despite their good performance characteristics, systolic systems can be hard to design because general global communication is prohibited. The first part of the thesis remedies this deficiency by providing a powerful methodology for designing systolic systems. It is shown that various kinds of global communication can be eliminated from a parallel system with virtually no performance penalty. In particular, if a systolic system has been augmented so that the host can broadcast to every processor in the system, the broadcasting can always be converted to local communication with almost no degradation in response time. Parallel systems can be designed with global communication and then converted to systolic systems, a methodology which is applied to the design of fast priority queues, counters, and pattern matchers. One of the designs is a device that dynamically shares its constituent processors among several fast priority queues so that no one queue overflows until the entire system overflows. In addition, it is shown that matrix computations--including matrix multiplication and LU-decomposition--can be performed by area-efficient systolic array algorithms. Having treated time-efficiency, the thesis next focuses on the question, "What interconnection structures have area-efficient layouts?" Good upper bounds for the area of layouts can be obtained for classes of graphs with good separator theorems. For example, any binary tree on n vertices has an O(n) area layout, and any bounded-degree planar graph has an O(nlg('2)n) area layout. The general algorithm that produces these layouts maintains a sparse representation for layouts that is based on the well-known UNION-FIND algorithm; as a result, the running time devoted to bookkeeping is nearly linear. Among the off-shoots of this work is an O(nlg('2)n) area chip which can implement an arbitrary tree of n vertices by making only n solder dot connections. Another result is a design for partitioning a complete binary tree into chips. Whereas the obvious packaging scheme requires two types of chips, one of which contains only a few nodes of the tree and has many off-chip connections, the new design requires only one type of chip which is packed full and has only four off-chip connections. The two parts of the thesis emphasize the contribution of communication to the performance and area of an integrated circuit. This concern complicates the classical model of parallel processing where communication is free and the measure of complexity is the number of operations. What is gained is a better understanding of integrated circuit computation in particular, and parallel computation in general. Combined, the two parts of the thesis provide mathematical views of an engineering discipline: techniques of theoretical computer science--e.g., divide and conquer, automata theory, asymptotic analysis--applied to integrated circuit computation.

The network architecture of the Connection Machine CM-5 (extended abstract)

Abstract: The Connection Machine Model CM-5 Supercomputer is a massively parallel computer system designed to offer performance in the range of 1 teraflops (1012 floating-point operations per second). The CM-5 obtains its high performance while offering ease of programming, flexibility, and reliability. The machine contains three communication networks: a data network, a control network, and a diagnostic network. This paper describes the organization of these three networks and how they contribute to the design goals of the CM-5.

Handbook of Applied Cryptography

Abstract: From the Publisher: A valuable reference for the novice as well as for the expert who needs a wider scope of coverage within the area of cryptography, this book provides easy and rapid access of information and includes more than 200 algorithms and protocols; more than 200 tables and figures; more than 1,000 numbered definitions, facts, examples, notes, and remarks; and over 1,250 significant references, including brief comments on each paper.

ROUGE: A Package for Automatic Evaluation of Summaries

Abstract: ROUGE stands for Recall-Oriented Understudy for Gisting Evaluation. It includes measures to automatically determine the quality of a summary by comparing it to other (ideal) summaries created by humans. The measures count the number of overlapping units such as n-gram, word sequences, and word pairs between the computer-generated summary to be evaluated and the ideal summaries created by humans. This paper introduces four different ROUGE measures: ROUGE-N, ROUGE-L, ROUGE-W, and ROUGE-S included in the ROUGE summarization evaluation package and their evaluations. Three of them have been used in the Document Understanding Conference (DUC) 2004, a large-scale summarization evaluation sponsored by NIST.

RADAR: an in-building RF-based user location and tracking system

Abstract: The proliferation of mobile computing devices and local-area wireless networks has fostered a growing interest in location-aware systems and services. In this paper we present RADAR, a radio-frequency (RF)-based system for locating and tracking users inside buildings. RADAR operates by recording and processing signal strength information at multiple base stations positioned to provide overlapping coverage in the area of interest. It combines empirical measurements with signal propagation modeling to determine user location and thereby enable location-aware services and applications. We present experimental results that demonstrate the ability of RADAR to estimate user location with a high degree of accuracy.

A program for annotating and predicting the effects of single nucleotide polymorphisms, SnpEff: SNPs in the genome of Drosophila melanogaster strain w1118; iso-2; iso-3

Abstract: We describe a new computer program, SnpEff, for rapidly categorizing the effects of variants in genome sequences. Once a genome is sequenced, SnpEff annotates variants based on their genomic locations and predicts coding effects. Annotated genomic locations include intronic, untranslated region, upstream, downstream, splice site, or intergenic regions. Coding effects such as synonymous or non-synonymous amino acid replacement, start codon gains or losses, stop codon gains or losses, or frame shifts can be predicted. Here the use of SnpEff is illustrated by annotating ~356,660 candidate SNPs in ~117 Mb unique sequences, representing a substitution rate of ~1/305 nucleotides, between the Drosophila melanogaster w1118; iso-2; iso-3 strain and the reference y1; cn1 bw1 sp1 strain. We show that ~15,842 SNPs are synonymous and ~4,467 SNPs are non-synonymous (N/S ~0.28). The remaining SNPs are in other categories, such as stop codon gains (38 SNPs), stop codon losses (8 SNPs), and start codon gains (297 SNPs) in...