Charles Trullemans

Bio: Charles Trullemans is an academic researcher from Université catholique de Louvain. The author has contributed to research in topics: Reduced instruction set computing & Fault coverage. The author has an hindex of 4, co-authored 11 publications receiving 134 citations.

A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor

Abstract: A carry-free division algorithm is described. It is based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full adder. Its application to a 1024-b RSA (Rivest, Shamir, and Adelman) cryptographic chip is presented. The features of this new algorithm allowed high performance (8 kb/s for 1024-b words) to be obtained for relatively small area and power consumption (80 mm/sup 2/ in a 2- mu m CMOS process and 500 mW at 25 MHz). >

From KCL to Class D Amplifier

Abstract: From a circuit point of view, the starting point of the students coming out of the secondary school is roughly limited to describing the flow of electrical charges through a simple loop Nevertheless, one and a half years later, they can design, simulate, build and test the core of a Class D amplifier while meeting demanding learning objectives This paper relates the story of a project conducted in the context of an undergraduate electrical engineering program Circuits and system concepts are introduced from the beginning of the first year in a physics course, and are applied to a project during the second term A circuit theory course and the Class D amplifier project are run in parallel during the second term of the second year Effective learning is facilitated by a mixture of lectures covering the necessary concepts and self- directed laboratory experiments allowing active acquisition of problem solving skills At the end of the project, enthusiastic students can listen to the sound of their MP3 player through the amplifier that results from their teamwork A survey indicates that the outcomes of the project are in line with the expected results of a problem- and project-based learning environment

Logic Verification of Incomplete Functions and Design Error Location

Abstract: At the stage of logic verification, it is necessary not only to detect but also to locate the sources of design errors that may exist in the gate-level circuit. For an incompletely specified function, a method to compute the corresponding 3-terminal BDD that represents the ON-set, OFF-set and DC-set, is described. Two incomplete functions are equivalent if, and only if, their 3-terminal BDDs are isomorphic. If the gate-level circuit is verified to be incorrect, a conditional stuck-at fault model is proposed to represent the circuit with design errors. The incorrect logic values at the design error sites can be considered as conditional stuck-at faults. A design error locating method, based on fault simulation and released pattern generation, is described.

Apprentissage par projet en électricité (partie 1): Conception et réalisation d’un système de filoguidage électromagnétique

Abstract: La formation d’ingenieur a l’Universite catholique de Louvain a ete reorganisee selon un principe de pedagogie active (apprentissage par problemes et par projets). Ainsi, il est propose aux etudiants qui entament leur specialisation en electricite ou en electromecanique, un projet leur permettant d’aborder a la fois les notions d’electromagnetisme et les notions de circuits electriques et de faire le lien entre ces deux matieres. Dans cet article, nous presentons en details un de ces projets, consistant pour les etudiants a realiser un capteur de suivi de ligne, ainsi que son electronique de traitement. Des variantes sont egalement exposees, s’articulant autour de differents types de capteurs integres. Nous detaillons les moyens et l’approche mis en oeuvre et tirons les conclusions relatives a l’organisation de ces projets.

Apprentissage par projet en électricité : exemples et mise en oeuvre

Abstract: La formation d'ingenieur a l'Universite catholique de Louvain a ete reorganisee selon un principe de pedagogie active (apprentissage par problemes et par projets). Ainsi, il est propose aux etudiants qui entament leur specialisation en electricite ou en electromecanique, un projet leur permettant d'aborder a la fois les notions d'electromagnetisme et les notions de circuits electriques et de faire le lien entre ces deux matieres. Dans cet article, nous presentons en details un de ces projets, consistant pour les etudiants a realiser un capteur de suivi de ligne, ainsi que son electronique de traitement. Des variantes sont egalement exposees, s'articulant autour de differents types de capteurs integres. Nous detaillons les moyens et l'approche mis en oeuvre et tirons les conclusions relatives a l'organisation de ces projets.

Optimal left-to-right binary signed-digit recoding

Abstract: This paper describes new methods for producing optimal binary signed-digit representations. This can be useful in the fast computation of exponentiations. Contrary to existing algorithms, the digits are scanned from left to right (i.e., from the most significant position to the least significant position). This may lead to better performances in both hardware and software.

The differential CORDIC algorithm: Constant scale factor redundant implementation without correcting iterations

Abstract: The CORDIC algorithm is a well-known iterative method for the efficient computation of vector rotations, and trigonometric and hyperbolic functions. Basically, CORDIC performs a vector rotation which is not a perfect rotation, since the vector is also scaled by a constant factor. This scaling has to be compensated for following the CORDIC iteration. Since CORDIC implementations using conventional number systems are relatively slow, current research has focused on solutions employing redundant number systems which make a much faster implementation possible. The problem with these methods is that either the scale factor becomes variable, making additional operations necessary to compensate for the scaling, or additional iterations are necessary compared to the original algorithm. In contrast we developed transformations of the usual CORDIC algorithm which result in a constant scale factor redundant implementation without additional operations. The resulting "Differential CORDIC Algorithm" (DCORDIC) makes use of on-line (most significant digit first redundant) computation. We derive parallel architectures for the radix-2 redundant number systems and present some implementation results based on logic synthesis of VHDL descriptions produced by a DCORDIC VHDL generator. We finally prove that, due to the lack of additional operations, DCORDIC compares favorably with the previously known redundant methods in terms of latency and computational complexity.

High-radix modular multiplication for cryptosystems

Abstract: Two algorithms for modular multiplication with very large moduli are analyzed specifically for their applicability when a high radix is used for the multiplier. Both algorithms perform modulo reductions interleaved with the addition of partial products; one algorithm is using the standard residue system, whereas the other utilizes a nonstandard system using reductions modulo a power of the base. The emphasis is on situations, as in cryptosystems, where modular exponentiation is to be realized by many repeated modular multiplications on very large operands, e.g., for cryptosystems with key lengths of 500-1000 b. >

A radix-4 modular multiplication hardware algorithm for modular exponentiation

Abstract: A fast radix-4 modular multiplication hardware algorithm is proposed. It is efficient for modular exponentiation with a large modulus, used in public-key cryptosystems such as the RSA cryptosystem. The operands and the result of multiplication which are intermediate results in modular exponentiation are represented in a redundant representation. The computation proceeds in serial-parallel fashion. Each subtraction for the division for residue calculation is embedded in the repeated multiply-add. Each intermediate result is represented in a more redundant representation than that for the operands and the result, so that the number of the required addition/subtractions is reduced. All addition/subtraction are carried out without carry propagation. A serial-parallel modular multiplier based on the algorithm has a regular cellular array structure with a bit slice feature and is suitable for VLSI implementation. >

A fast VLSI adder architecture

Abstract: An architecture for performing fixed-point, high-speed, two's-complement, bit-parallel addition by using the carry-free property of redundant arithmetic and a fast parallel redundant-to-binary conversion scheme is presented. The internal numbers are represented in radix-2 redundant digit form, and the inputs and the output of the adder are represented in two's-complement binary form. The adder operands are added first in a radix-2 redundant adder to produce the result in radix-2 digit (-1, 0, 1) form. This result is converted to two's-complement binary form using the parallel conversion scheme. The high-speed conversion for long words is achieved through the use of a novel sign-select operation. The proposed adder, referred to as the sign-select conversion adder, is faster than all previous high-speed two's-complement binary adders for large word lengths. The implementation is highly regular with repeated modules and is very well suited for VLSI implementation. >