An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

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FinFETs and Other Multi-Gate Transistors

Condition monitoring (CM) has already been proven to be a cost effective means of enhancing reliability and improving customer service in power equipment, such as transformers and rotating electrical machinery. CM for power semiconductor devices in power electronic converters is at a more embryonic stage; however, as progress is made in understanding semiconductor device failure modes, appropriate sensor technologies, and signal processing techniques, this situation will rapidly improve. This technical review is carried out with the aim of describing the current state of the art in CM research for power electronics. Reliability models for power electronics, including dominant failure mechanisms of devices are described first. This is followed by a description of recently proposed CM techniques. The benefits and limitations of these techniques are then discussed. It is intended that this review will provide the basis for future developments in power electronics CM.

Condition Monitoring for Device Reliability in Power Electronic Converters: A Review

Introduction to Mathematical Statistics. By R.V. Hogg and A. T. Craig. Pp. ix, 245. 47s. 1959. (The Macmillan Company, New York)

In an array of solid-state memory cells organized into rows and segmented columns and addressable by wordlines and bit lines, a memory cell within a segmented column is addressable by segment-select transistors which selectively connect the memory cell's pair of bit lines via conductive lines running parallel to the columns to a column decode circuit. The disposition of the segment-select transistors and the conductive lines relative to the segmented columns enables one segment-select transistor to fit in every two or more columns. In one embodiment, the segment-select transistors have double the pitch of the columns while the conductive lines have the same pitch of the columns. In another embodiment, the segment-select transistor have four times the pitch of the columns while the conductive lines have double the pitch of the columns. This enables the use of larger size segment-select transistors which are necessary for passing higher currents in devices such as EPROM or flash EEPROM. Column segmentation effectively isolates defects to individual segments and reduces the capacitance in the source and drain of an address memory cell.

Segmented column memory array

A dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported. The authors discuss the gate coupling phenomenon for NMOS transistors and its effect under ESD transient conditions. A dynamic gate-coupled device was studied to understand the gate coupling effect. The authors present the complete phenomena and results for nonsilicided devices as well as for silicided structures. The measured ESD stress results are given. The gate coupling effect and device operation under ESD are explained by using modeling and simulation results. The design issues for optimum output ESD protection are also discussed. >

Dynamic gate coupling of NMOS for efficient output ESD protection

A circuit-level simulator for ESD and EOS is presented. Equations for modeling the high current behavior of NMOS and PMOS transistors have been developed and implemented in SPICE. A simple and practical extraction methodology for obtaining the bipolar parameters is given, which uses the three terminal currents obtained from a single high current I-V curve. Simulation results are presented and compared to experimental data for single devices as well as a practical output circuit.

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

The effect of salicides and the influence of the local substrate potential on ESD performance of deep submicron nMOS transistors have been studied. It is shown that salicidation causes a strong dependence of ESD performance on effective channel length in these devices. Salicides also impact the behavior of the lateral npn parasitic bipolar transistor by affecting the emitter efficiency. A higher local substrate potential has been shown to have a positive impact on ESD performance. Based on these results we have designed and demonstrated a substrate triggered nMOS protection circuit which provides >2 kV ESD performance in a fully salicided process.

Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes

The use of a substrate pump to achieve uniform npn protection in a multi-finger NMOS is reported for advanced CMOS technologies with silicide. The novel feature of this device technique is the implementation of a floating guardring to effectively pump the local substrate of the protection NMOS. SPICE simulations are presented to illustrate the device concept as well as the device design optimization.

Substrate pump NMOS for ESD protection applications

Input/output electrostatic discharge (ESD) circuit requirements call for good protection of the pin with respect to both the ground and the power bus pins. Although effective protection can be designed at the pin many cases of damage phenomena are known to occur internal to the chip beyond the protection circuit. Here, the issues of protection between V/sub DD/ and V/sub SS/ are discussed first. This is followed by examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design. Several illustrative actual case studies are reported to emphasize the internal chip ESD phenomena and their adverse effects. >

Charvaka Duvvury

Papers

Dynamic gate coupling of NMOS for efficient output ESD protection

Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations

Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes

Substrate pump NMOS for ESD protection applications

Internal chip ESD phenomena beyond the protection circuit