Built in self-test (BIS T) modules are essential devices in various application, which includes microprocessors, microcontroller, multi-core system, and multi-processor systems. The conventional BIS T modules are failed to solve the pro blems presented in various memories, which are affected by the stuck at faults. Therefore, this work is focused on implementation of a Hybrid Memory Logic (HML)-BIS T, which is used to detect and correct the errors presented in the memory elements. Initially, linear feedback shift register (LFS R) modules introduced for generating the random test patterns for write address, read address and write data. Here, activity factor is used to generate the non-repeated random numbers from LFSR Then, the data stored in memory are compared with original source data using space comparator. Finally, the BIS T module corrects the memory for various test cases. The simulations revealed that the proposed HML-BIS T method resulted in better area, delay, power performance as compared to conventional MBIST [16], PSRG-BIST [15], and FT-BIST [14] approaches.

Design of Hybrid Memory Built in Self Test using Linear Feedback Shift Registers

Nanoscale interlayer vias (ILVs) in monolithic 3-D (M3D) ICs have enabled high-density vertical integration of logic and memory tiers. However, the sequential assembly of M3D tiers via wafer bonding is prone to variability in the immature fabrication process and manufacturing defects. The yield degradation due to ILV faults can be mitigated via dedicated test and diagnosis of ILVs using built-in self-test (BIST). Prior work has carried out fault localization for a regular 1-D placement of ILVs in the M3D layout where shorts are assumed to arise only between unidirectional ILVs. However, to minimize wirelength in M3D routing, ILVs may be irregularly placed by a place-and-route tool, and shorts can also occur between an up-going ILV and a down-going ILV. To test and localize faults in realistic ILV layouts, we present a new BIST framework that is optimized for test time and PPA overhead. We also present a graph-theoretic approach for representing potential fault sites in the ILVs and carry out inductive fault analysis to drop noncritical sites. We describe a procedure for optimally assigning ILVs to the BIST pins and determining the BIST configuration for test-cost minimization. Evaluation results for M3D benchmarks demonstrate the effectiveness of the proposed framework. 

Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs

Built in self-test (BIST) modules are essential devices in various application, which includes microprocessors, microcontroller, multi-core system, and multi-processor systems. The conventional BIST modules are failed to solve the problems presented in various memories, which are affected by the stuck at faults. Therefore, this work is focused on implementation of a Hybrid Memory Logic (HML)-BIST, which is used to detect and correct the errors presented in the memory elements. Initially, linear feedback shift register (LFSR) modules introduced for generating the random test patterns for write address, read address and write data. Here, activity factor is used to generate the non-repeated random numbers from LFSR. Then, the data stored in memory are compared with original source data using space comparator. Finally, the BIST module corrects the memory for various test cases. The simulations revealed that the proposed HML-BIST method resulted in better area, delay, power performance as compared to conventional MBIST [16], PSRG-BIST [15], and FT-BIST[14] approaches.

Implementation of Power Binning-based Logic BIST Control using Activity Factor

Aggressive GPU cache bypassing with monolithic 3D-based NoC

Resistive random-access memory (RRAM) constitutes a promising technology for next-generation memory architectures due to its simple structure, high on/off ratio, and processing-in-memory ability. Its compatibility with emerging monolithic 3D (M3D) integration enables extremely high density using monolithic inter-tier vias (MIVs). However, both RRAM and M3D are susceptible to high defect rates due to immature manufacturing processes and process variations. Fault diagnosis for M3D-integrated RRAM and MIVs is therefore necessary to facilitate yield learning. In this work, we present a detailed characterization of RRAM faulty behaviors in the presence of process variations and manufacturing defects. We develop a diagnosis procedure by identifying appropriate reference resistance based on RRAM characteristics to efficiently distinguish fault origins. Results show that the proposed solution is compatible with existing test algorithms to significantly improve diagnostic resolution without affecting fault coverage.

Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration

Monolithic 3D (M3D) integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-lay...

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and ...

ChaudhuriArjun

Papers

Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

Design Automation and Test Solutions for Monolithic 3D ICs