Cheisan J. Yue

Bio: Cheisan J. Yue is an academic researcher from Honeywell. The author has contributed to research in topics: Subthreshold conduction & Threshold voltage. The author has an hindex of 1, co-authored 1 publications receiving 24 citations.

Method for electrically characterizing the insulator in SOI devices

Abstract: A rapid method for determining electrical characteristics of SOI wafers whereby the silicon substrate acts as a gate and tungsten probes make a source and drain connection at the top silicon surface to form a point contact transistor. Drain current is measured as a function of gate voltage as gate voltage is swept from negative to positive values. The subthreshold voltage current characteristic exhibits a minimum drain current occurring close to zero gate voltage. The tungsten probe point contacts apparently are responding to both electron and hole conduction or simply intrinsic CMOS behavior. Using current voltage characteristics, estimates may be made of interface state density and oxide charge density. Analysis of the gate voltage shift for minimum drain current allows determination of threshold voltage shift due to radiation.

Vehicular rearview mirror with blind spot viewing system

Abstract: A vehicular exterior rearview mirror blind spot viewing system includes an exterior rearview mirror assembly which enables moving the reflective mirror element to an alternate position for viewing of areas adjacent the vehicle which otherwise would be hidden in the driver's blind spot. The blind spot system includes a reflective mirror element mounted on a pivot member such as an electric actuator for adjusting the field of view of the mirror element for different drivers about an axis which is preferably centered on the mirror element. A support member has a joint spaced laterally of the axis and pivotally connected to the pivot member for moving the mirror element between a first rearward viewing position and a blind spot viewing position. A power source such as an electric motor is preferably mounted on the pivot member and is spaced from the support member joint, and includes a threaded member pivotally connected to the support member and driven by a gear. The electric motor is preferably connected via a control circuit to a remote switch such as in the passenger compartment to allow the driver to pivot the support member and mirror element for blind spot viewing when desired.

Charge separation techniques for irradiated pseudo-MOS SOI transistors

Abstract: Pseudo-metal-oxide-semiconductor (MOS) silicon-on-insulator (SOI) transistors are used to study the total ionizing dose response of buried oxides. The concentrations of radiation-induced oxide-trap and interface-trap charge are separated using midgap and dual-transistor charge separation analysis techniques. Dual-transistor analysis is shown to be especially well suited for charge separation of pseudo-MOSFETs (/spl Psi/-MOSFETs) because the electron conduction mode of this simple point-contact device resembles an nMOS transistor, and the hole conduction mode resembles a pMOS transistor. That this is a single device ensures that the dual-transistor assumption of equal oxide-trap charge in otherwise identical n and pMOS transistors is satisfied automatically. Both electron and hole conduction current-voltage (I-V) traces must extrapolate to a common, physically realistic midgap voltage; this is employed as a test for the self-consistency of /spl Psi/-MOSFET data. Charge separation performed using midgap and dual-transistor analyses show good agreement for the devices employed in this paper.

Defect induced buried oxide (DIBOX) for throughput SOI

Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing a first low energy implantation step to create a stable defect region; a second low energy implantation step to create an amorphous layer adjacent to the stable defect region; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising said semiconductor substrate having said DIBOX is also provided herein.

Implantation process using sub-stoichiometric, oxygen doses at different energies

Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of substoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2 x 107 cm-2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.

Semiconductor Device and Method of Manufacturing the Same

Abstract: In manufacturing a semiconductor device, static electricity is generated while contact holes are formed in an interlayer insulating film by dry etching. Damage to a pixel region or a driving circuit region due to travel of the static electricity generated is prevented. Gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.