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Chen-Han Chien

Bio: Chen-Han Chien is an academic researcher from University of Zurich. The author has contributed to research in topics: Signal processing & Delta modulation. The author has an hindex of 2, co-authored 2 publications receiving 64 citations.

Papers
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Journal ArticleDOI
TL;DR: A 0.5V 55μW 64×2-channel binaural silicon cochlea aiming for ultra-low-power IoE applications like event-driven VAD, sound source localization, speaker identification and primitive speech recognition is presented.
Abstract: This paper presents a $64 \times 2$ channel stereo-audio sensing front end with parallel asynchronous event output inspired by the biological cochlea. Each binaural channel performs feature extraction by analog bandpass filtering, and the filtered signal is encoded into events via asynchronous delta modulation (ADM). The channel central frequencies $f_{0}$ are geometrically scaled across the human hearing range. Two design techniques are highlighted to achieve the high system power efficiency: source-follower-based bandpass filters (BPFs) and asynchronous delta modulation (ADM) with adaptive self-oscillating comparison. The chip was fabricated in 0.18 $\mu \text{m}$ 1P6M CMOS, and occupies an area of $10.5 \times 4.8$ mm2. The core cochlea system operating under a 0.5 V power supply consumes 55 $\mu \text{W}$ at an output rate of 100k event/s. The measured range of $f_{0}$ is from 8 Hz to 20 kHz, and the BPF quality factor ${Q}$ can be tuned from 1 to almost 40. The 1 $\sigma $ mismatch of $f_{0}$ and ${Q}$ between two ears is 3.3% and 15%, respectively, across all channels at ${Q}\approx $ 10. Reconstruction of speech input from the event output of the chip is performed to validate the information integrity in event-domain representation, and vowel discrimination is demonstrated as a simple application using histograms of the output events. This type of silicon cochlea front end targets integration with embedded event-driven processors for low-power smart audio sensing with classification capabilities, such as voice activity detection and speaker identification.

62 citations

Proceedings ArticleDOI
25 Feb 2016
TL;DR: A 0.5V 55µW 64×2-channel binaural silicon cochlea aiming for ultra-low-power IoE applications like event-driven VAD, sound source localization, speaker identification and primitive speech recognition is presented.
Abstract: Event-driven DSPs have the advantage of activity-dependent power consumption [1], and event-driven neural networks have shown superior power efficiency in real-time recognition tasks [2]. A bio-inspired silicon cochlea [3] functionally transforms sound input into multi-frequency-channel asynchronous event output, and hence is the natural candidate for the audio sensing frontend of event-driven signal processing systems like [1] and [2]. High-quality event encoding can be implemented as level-crossing (LC) ADCs, but the circuits are area- and power-inefficient [1]. Asynchronous delta modulation, the original form of LC sampling, on the other hand can be compactly realized even in small pixels of vision sensors [4]. Traditional audio processing employs digital FFTs and BPFs after signal acquisition by high-precision ADCs. However, it has been shown in [5] that for classification tasks like voice activity detection (VAD), good accuracy can still be attained when filtering is performed using low-power analog BPFs. This paper presents a 0.5V 55µW 64×2-channel binaural silicon cochlea aiming for ultra-low-power IoE applications like event-driven VAD, sound source localization, speaker identification and primitive speech recognition. The source-follower-based BPF and the asynchronous delta modulator (ADM) with adaptive self-oscillating comparison for event encoding are highlighted for the advancement of the system power efficiency.

24 citations


Cited by
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Journal ArticleDOI
TL;DR: A brief history of neuromorphic engineering is presented, some of the principal current large-scale projects, their main features, how their approaches are complementary and distinct, their advantages and drawbacks, and highlight the sorts of capabilities that each can deliver to neural modellers are highlighted.
Abstract: Neuromorphic computing covers a diverse range of approaches to information processing all of which demonstrate some degree of neurobiological inspiration that differentiates them from mainstream conventional computing systems. The philosophy behind neuromorphic computing has its origins in the seminal work carried out by Carver Mead at Caltech in the late 1980s. This early work influenced others to carry developments forward, and advances in VLSI technology supported steady growth in the scale and capability of neuromorphic devices. Recently, a number of large-scale neuromorphic projects have emerged, taking the approach to unprecedented scales and capabilities. These large-scale projects are associated with major new funding initiatives for brain-related research, creating a sense that the time and circumstances are right for progress in our understanding of information processing in the brain. In this review we present a brief history of neuromorphic engineering then focus on some of the principal current large-scale projects, their main features, how their approaches are complementary and distinct, their advantages and drawbacks, and highlight the sorts of capabilities that each can deliver to neural modellers.

275 citations

Journal ArticleDOI
TL;DR: In this article , the authors present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of the neuromorphic computing community.
Abstract: Abstract Modern computation based on von Neumann architecture is now a mature cutting-edge science. In the von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer is responsible for a large part of the power consumption. The next generation computer technology is expected to solve problems at the exascale with 10 18 calculations each second. Even though these future computers will be incredibly powerful, if they are based on von Neumann type architectures, they will consume between 20 and 30 megawatts of power and will not have intrinsic physically built-in capabilities to learn or deal with complex data as our brain does. These needs can be addressed by neuromorphic computing systems which are inspired by the biological concepts of the human brain. This new generation of computers has the potential to be used for the storage and processing of large amounts of digital information with much lower power consumption than conventional processors. Among their potential future applications, an important niche is moving the control from data centers to edge devices. The aim of this roadmap is to present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of neuromorphic technology, namely materials, devices, neuromorphic circuits, neuromorphic algorithms, applications, and ethics. The roadmap is a collection of perspectives where leading researchers in the neuromorphic community provide their own view about the current state and the future challenges for each research area. We hope that this roadmap will be a useful resource by providing a concise yet comprehensive introduction to readers outside this field, for those who are just entering the field, as well as providing future perspectives for those who are well established in the neuromorphic computing community.

99 citations

Journal ArticleDOI
TL;DR: A survey of recent works in developing neuromorphic or neuro-inspired hardware systems, focusing on those systems which can either learn from data in an unsupervised or online supervised manner, and present algorithms and architectures developed specially to support on-chip learning.
Abstract: In this paper, we present a survey of recent works in developing neuromorphic or neuro-inspired hardware systems. In particular, we focus on those systems which can either learn from data in an unsupervised or online supervised manner. We present algorithms and architectures developed specially to support on-chip learning. Emphasis is placed on hardware friendly modifications of standard algorithms, such as backpropagation, as well as novel algorithms, such as structural plasticity, developed specially for low-resolution synapses. We cover works related to both spike-based and more traditional non-spike-based algorithms. This is followed by developments in novel devices, such as floating-gate MOS, memristors, and spintronic devices. CMOS circuit innovations for on-chip learning and CMOS interface circuits for post-CMOS devices, such as memristors, are presented. Common architectures, such as crossbar or island style arrays, are discussed, along with their relative merits and demerits. Finally, we present some possible applications of neuromorphic hardware, such as brain–machine interfaces, robotics, etc., and identify future research trends in the field.

90 citations

Journal ArticleDOI
01 Dec 2020-PhotoniX
TL;DR: The need and the possibility to conceive a photonic memristor are discussed, a positive outlook on the challenges and opportunities for the ambitious goal of realising the next generation of full-optical neuromorphic hardware is offered.
Abstract: Neuromorphic computing applies concepts extracted from neuroscience to develop devices shaped like neural systems and achieve brain-like capacity and efficiency. In this way, neuromorphic machines, able to learn from the surrounding environment to deduce abstract concepts and to make decisions, promise to start a technological revolution transforming our society and our life. Current electronic implementations of neuromorphic architectures are still far from competing with their biological counterparts in terms of real-time information-processing capabilities, packing density and energy efficiency. A solution to this impasse is represented by the application of photonic principles to the neuromorphic domain creating in this way the field of neuromorphic photonics. This new field combines the advantages of photonics and neuromorphic architectures to build systems with high efficiency, high interconnectivity and high information density, and paves the way to ultrafast, power efficient and low cost and complex signal processing. In this Perspective, we review the rapid development of the neuromorphic computing field both in the electronic and in the photonic domain focusing on the role and the applications of memristors. We discuss the need and the possibility to conceive a photonic memristor and we offer a positive outlook on the challenges and opportunities for the ambitious goal of realising the next generation of full-optical neuromorphic hardware.

87 citations

Journal ArticleDOI
TL;DR: This work investigates the effectiveness of synchronous and asynchronous frame-based features generated using spike count and constant event binning in combination with the use of a recurrent neural network for solving a classification task using N-TIDIGITS18 dataset and proposes a new pre-processing method which applies an exponential kernel on the output cochlea spikes so that the interspike timing information is better preserved.
Abstract: Event-driven neuromorphic spiking sensors such as the silicon retina and the silicon cochlea encode the external sensory stimuli as asynchronous streams of spikes across different channels or pixels. Combining state-of-art deep neural networks with the asynchronous outputs of these sensors has produced encouraging results on some datasets but remains challenging. While the lack of effective spiking networks to process the spike streams is one reason, the other reason is that the pre-processing methods required to convert the spike streams to frame-based features needed for the deep networks still require further investigation. This work investigates the effectiveness of synchronous and asynchronous frame-based features generated using spike count and constant event binning in combination with the use of a recurrent neural network for solving a classification task using N-TIDIGITS18 dataset. This spike-based dataset consists of recordings from the Dynamic Audio Sensor, a spiking silicon cochlea sensor, in response to the TIDIGITS audio dataset. We also propose a new pre-processing method which applies an exponential kernel on the output cochlea spikes so that the interspike timing information is better preserved. The results from the N-TIDIGITS18 dataset show that the exponential features perform better than the spike count features, with over 91% accuracy on the digit classification task. This accuracy corresponds to an improvement of at least 2.5% over the use of spike count features, establishing a new state of the art for this dataset.

87 citations