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Chen-Hao Hsu

Bio: Chen-Hao Hsu is an academic researcher from National Taiwan University. The author has contributed to research in topics: Routing (electronic design automation) & Quantum circuit. The author has an hindex of 2, co-authored 3 publications receiving 21 citations.

Papers
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Proceedings ArticleDOI
05 Nov 2018
TL;DR: A novel initial detailed routing algorithm to consider industrial design-rule constraints and optimize the total wirelength and via count and outperforms all the winning teams of the 2018 ACM ISPD Initial Detailed Routing Contest.
Abstract: Detailed routing is the most complicated and time-consuming stage in VLSI design and has become a critical process for advanced node enablement. To handle the high complexity of modern detailed routing, initial detailed routing is often employed to minimize design-rule violations to facilitate final detailed routing, even though it is still not violation-free after initial routing. This paper presents a novel initial detailed routing algorithm to consider industrial design-rule constraints and optimize the total wirelength and via count. Our algorithm consists of three major stages: (1) an effective pin-access point generation method to identify valid points to model a complex pin shape, (2) a via-aware track assignment method to minimize the overlaps between assigned wire segments, and (3) a detailed routing algorithm with a novel negotiation-based rip-up and re-route scheme that enables multithreading and honors global routing information while minimizing design-rule violations. Experimental results show that our router outperforms all the winning teams of the 2018 ACM ISPD Initial Detailed Routing Contest, where the top-3 routers result in 23%, 52%, and 1224% higher costs than ours.

23 citations

Journal ArticleDOI
02 Jun 2019
TL;DR: This algorithm consists of a bus clustering method to reduce the routing complexity, a DAG-based algorithm to connect a bus in the specific topology, and a rip-up and re-route scheme to alleviate the routing congestion.
Abstract: As clock frequencies increase, topology-matching bus routing is desired to provide an initial routing result which facilitates the following buffer insertion to meet the timing constraints. In this article, we present a complete topology-matching bus routing framework considering nonuniform track configurations. In the framework, a bus clustering technique is proposed to reduce the routing complexity by grouping buses sharing similar pin locations. To perform topology-matching routing in a nonuniform track configuration, we propose a directed acyclic graph-based algorithm to connect a bus in a specific topology. Furthermore, a rip-up and reroute scheme is applied to alleviate the routing congestion. Compared with the state-of-the-art topology-matching bus routers, our proposed algorithm significantly improves the routing quality and reduces the number of spacing violations in comparable runtime.

9 citations

Proceedings ArticleDOI
05 Dec 2021
TL;DR: Wang et al. as mentioned in this paper presented the first work that can automatically perform bridge compression on topological quantum error correction (TQEC) circuits, which can averagely reduce space-time volumes by 83%.
Abstract: The topological quantum error correction (TQEC) scheme is promising for scalable and reliable quantum computing. A TQEC circuit can be modeled by a three-dimensional diagram, and the implementation resource of a TQEC circuit is abstracted to its space-time volume. Implementing a quantum algorithm with a reasonable physical qubit number and reasonable computation time is challenging for large-scale practical problems. Therefore, minimizing the space-time volume of a TQEC circuit becomes a crucial issue. Previous work shows that bridge compression can greatly compress TQEC circuits, but it was performed only manually. It is desirable to develop automated compression techniques for TQEC circuits to achieve low-overhead, large-scale quantum computations. In this paper, we present the first work that can automatically perform bridge compression on TQEC circuits. Compared with the state-of-the-art method, experimental results show that our proposed algorithm can averagely reduce space-time volumes by 83%.

2 citations

Journal ArticleDOI
TL;DR: Wang et al. as mentioned in this paper proposed a bridge compression technique to compact TQEC circuits with modularization, and they also proposed a time-ordering-aware 2.5D placement for compacting TQec circuits and satisfying time-ordered measurement constraints.
Abstract: Topological quantum error correction (TQEC) is promising for scalable fault-tolerant quantum computation. The required resource of a TQEC circuit can be modeled as its space-time volume of a three-dimensional geometric description. Implementing a quantum algorithm with a reasonable physical qubit number and computation time is challenging for large-scale complex problems. Therefore, it is desirable to minimize the space-time volume for large-scale TQEC circuits. Previous work proposed bridge compression, which can significantly compress a TQEC circuit, but it was performed manually. This article presents the first automated tool that can perform bridge compression on a large-scale TQEC circuit. Our proposed algorithm applies the bridge compression technique to compactify TQEC circuits with modularization. Besides, we offer a time-ordering-aware 2.5-D placement for compacting TQEC circuits and satisfying time-ordered measurement constraints. On the other hand, we suggest friend net-aware routing to effectively reduce the required routing resource under topological deformation. Compared with the state-of-the-art work, experimental results show that our proposed algorithm can averagely reduce space-time volumes by 84%.

Cited by
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Proceedings ArticleDOI
01 Nov 2019
TL;DR: This paper proposes a detailed router that judiciously handles hard-to-access pins and new design rules including length-dependent parallel run length spacing, end-of-line spacing with parallel edges, and corner- to-corner spacing that can effectively reduce the number of violations with comparable wirelength.
Abstract: Detailed routing becomes a crucial challenge in VLSI design with shrinking feature size and increasing design complexity. More complicated design rules were added to guarantee manufacturability, which made detailed routing an even harder task to achieve in the design flow. In this paper, we propose a detailed router that judiciously handles hard-to-access pins and new design rules including length-dependent parallel run length spacing, end-of-line spacing with parallel edges, and corner-to-corner spacing. Our experimental results show that our framework can effectively reduce the number of violations with comparable wirelength. Comparing our algorithm with the best score of each released designs in the ISPD'19 Contest, there is 2% score improvement. Compared with the state-of-the-art work [1], our algorithm achieves 69% better scores. The source code of Dr. CU 2.0 is available at https://github.com/cuhk-eda/dr-cu.

40 citations

Proceedings ArticleDOI
02 Nov 2020
TL;DR: A practical plug-in for routability optimization named PROS which can be applied in the state-of-the-art commercial EDA tool with negligible runtime overhead and achieve high accuracy of GR congestion prediction and significantly reduce design rule checking (DRC) violations.
Abstract: Recently the topic of routability optimization with prior knowledge obtained by machine learning techniques has been widely studied. However, limited by the prediction accuracy, the predictors of the existing related works can hardly be applied in a real-world EDA tool without extra runtime overhead for feature preparation. In this paper, we revisit this topic and propose a practical plug-in for routability optimization named PROS which can be applied in the state-of-the-art commercial EDA tool with negligible runtime overhead. PROS consists of an effective fully convolutional network (FCN) based predictor that only utilizes the data from placement result to forecast global routing (GR) congestion and a parameter optimizer that can reasonably adjust GR cost parameters based on prediction result to generate a better GR solution for detailed routing. Experiments on 19 industrial designs in advanced technology node show that PROS can achieve high accuracy of GR congestion prediction and significantly reduce design rule checking (DRC) violations by 11.65% on average.

36 citations

Proceedings ArticleDOI
04 Apr 2019
TL;DR: This work hosts the first detailed routing contest and releases a set of benchmarks synthesized by industrial tools with practical routing rules, and encourages participants to use double-cut vias to improve yield and result quality in this contest.
Abstract: Detailed routing becomes the most complicated and runtime consuming stage in the physical design flow as technology nodes advance. Due to the inaccessibility of advanced routing rules and industrial designs, it is hard to conduct detailed routing academic researches using the modern real-world designs. ISPD18 hosts the first detailed routing contest [1] and releases a set of benchmarks synthesized by industrial tools with practical routing rules. ISPD18 contest spurs detailed routing researches and provides students the opportunity to become familiar with the industrial designs and rules. On top of ISPD18 detailed routing contest, we host another detailed routing contest in ISPD19 [2] to consider several advanced routing rules and make the contest problem one step closer to the real-world routing challenges in advanced technology nodes. ISPD19 detailed routing contest encourages participants to use double-cut vias to improve yield and result quality. In addition, in order to drive the development of efficient routing frameworks, the deterministic multithreading feature is encouraged but optional in this contest.

26 citations

Proceedings ArticleDOI
01 Nov 2019
TL;DR: The ICCAD-2019 LEF/DEF-based open-source global routing contest revisits the global routing topic treated in the IS PD-2007 and ISPD-2008 contests, encouraging researchers to contribute open- source global routers that are industry-proven and well-correlated in advanced-node designs.
Abstract: In advanced nodes, routing has become more and more complicated. The ISPD-2018 and ISPD-2019 Initial Detailed Routing Contests [10] [11] were held to bridge the detailed routing gap between academia and industry by releasing benchmarks using industry tool and libraries. The industry-standard LEF/DEF-based benchmark suite has inspired a new generation of large-scale academic implementations of detailed routing frameworks considering complex design rules. At the same time, efforts such as the OpenROAD [1] and the IEEE CEDA DATC Robust Design Flow (RDF) [3] [8] projects aim to provide full RTL-to-GDS flows as the basis for academic research and improved academic-industry interfaces; the former project is moreover developed as open source. In these efforts, routing is clearly one of the most important stages. The ICCAD-2019 LEF/DEF-based open-source global routing contest revisits the global routing topic treated in the ISPD-2007 and ISPD-2008 contests [12] [13], encouraging researchers to contribute open-source global routers that are industry-proven and well-correlated in advanced-node designs.

25 citations

Proceedings ArticleDOI
Hao Chen1, Keren Zhu1, Mingjie Liu1, Xiyuan Tang1, Nan Sun1, David Z. Pan1 
02 Nov 2020
TL;DR: Experimental results demonstrate the efficiency and effectiveness of the approach in optimizing circuit performance while satisfying the specified constraints and post-layout simulations prove that the detailed routing results can achieve sign-off quality.
Abstract: Detailed routing is an intricate and tedious procedure in design automation and has become a crucial step for advanced node enablement. Compared with its advances in digital design, detailed routing for analog/mixed-signal (AMS) integrated circuits (ICs) is still heavily manual. In AMS designs, the sensitive net coupling issues and analog-specific constraints make detailed routing even more challenging. This work presents a novel and efficient detailed routing framework for automated AMS layout synthesis considering industrial design rules as well as analog-specific geometric and electrical constraints. Experimental results demonstrate the efficiency and effectiveness of our approach in optimizing circuit performance while satisfying the specified constraints. Post-layout simulations further prove that our detailed routing results can achieve sign-off quality.

22 citations