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Cheng-Hsin Chen

Bio: Cheng-Hsin Chen is an academic researcher from National Sun Yat-sen University. The author has contributed to research in topics: Transistor & MOSFET. The author has an hindex of 5, co-authored 19 publications receiving 68 citations.
Topics: Transistor, MOSFET, CMOS, Thin-film transistor, Dram

Papers
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Proceedings ArticleDOI
17 Dec 2010
TL;DR: In this article, a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications is proposed, where the buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process.
Abstract: In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (∼ 72%) and the retention time (∼ 50%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

18 citations

Proceedings ArticleDOI
13 Dec 2010
TL;DR: In this article, a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications is proposed, where the buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process.
Abstract: In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (∼ 84%) and the retention time (∼ 57%). 3. The thermal stability is drastically improved by its naturally formed source/drain tie. The above mentioned features help our proposed device structure to demonstrate the desired characteristics that are better than that of a conventional TFT. Additionally, the thermal instability is drastically improved which is good for long-term device operation.

18 citations

Journal ArticleDOI
TL;DR: In this article, a smiling poly-Si TFT was used to suppress the charge sharing and the source/drain-tied scheme can help to overcome the self-heating.
Abstract: One-transistor dynamic random access memory (1T-DRAM) thin-film transistor (TFT) could lead the revolution of system-on-panel application. However, no useful 1T-DRAM is fabricated on the polysilicon (poly-Si) thin film up to now. In this letter, we present a novel method to fabricate a smiling poly-Si TFT for 1T-DRAM applications. The experimental results show that the short-channel effects can be reduced because the smiling scheme is used to suppress the charge sharing and the source/drain-tied scheme can help to overcome the self-heating. Moreover, the device fabrication is fully compatible with current complementary metal-oxide-semiconductor (CMOS) technology.

7 citations

Proceedings ArticleDOI
17 Dec 2010
TL;DR: In this paper, the authors proposed a vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application, which can increase the pseudo-neutral region due to the bMPI under the vertical channel.
Abstract: This paper proposes a novel vertical MOSFET with the middle partial insulation and block oxide (bMPI) structure for 1T-DRAM application. The bMPI 1T-DRAM can increase the pseudo-neutral region due to the bMPI under the vertical channel and its device sensing current window is improved about 95% when compared to the planer bMPI 1T-DRAM. Because of the double gate structure, the proposed device has great gate controllability; hence, it can reduce the short-channel effects and enhance the electrical characteristics.

5 citations

Proceedings ArticleDOI
13 Dec 2010
TL;DR: In this paper, a performance comparison between junction and junctionless thin-film transistors (TFTs) by using TCAD simulations is presented, showing that the DIBL and S.S. of a junctionless TFT (JLTFT) are larger and higher, respectively, than those of its junction TFT counterpart.
Abstract: This paper for the first time presents a performance comparison between junction and junctionless thin-film transistors (TFTs) by using TCAD simulations. Note that the DIBL and S.S. of a junctionless TFT (JLTFT) are larger and higher, respectively, than those of its junction TFT (JTFT) counterpart. Although the JLTFT gets a higher current drive based on the same V ov as compared with the JTFT, its short-channel characteristics are worse and degraded. These results can be attributed to the fact that the major carriers in channel region for a JTFT make itself a barrier to carrier scattering, whereas, the JTFT does not have this problem, leading to get a high current drive. On the other hand, it may be owing to the grain boundary effects for a JLTFT to degrade its short-channel behavior. Fortunately, these results are still acceptable for scaled dimensions of TFTs.

5 citations


Cited by
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Patent
07 Feb 2011
TL;DR: In this paper, a semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell, a first region in electrical contact with the floating body, a second region in contact with said floating body and spaced apart from the first region, and a gate positioned between the first and second regions.
Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

67 citations

Patent
16 Apr 2015
TL;DR: In this article, a back bias is applied to the memory cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cells.
Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

65 citations

Patent
29 Oct 2010
TL;DR: In this paper, a semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory and non-volatile memory.
Abstract: Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

55 citations

Patent
26 May 2011
TL;DR: In this article, a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a nonvolatile memory comprising a resistance change element configured to stores data stored in the floating body under any one of a plurality of predetermined conditions.
Abstract: Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.

42 citations

Journal ArticleDOI
TL;DR: In this article, the characteristics and sensitivities of p-type junctionless gate-all-around (GAA) nanowire transistors are demonstrated by simulating a 3D quantum transport device with a view to their use in CMOS technology.
Abstract: The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (Vth), on current (Ion), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.

41 citations