C
Cheng-Wen Wu
Researcher at National Tsing Hua University
Publications - 321
Citations - 6742
Cheng-Wen Wu is an academic researcher from National Tsing Hua University. The author has contributed to research in topics: Fault coverage & Fault (power engineering). The author has an hindex of 41, co-authored 317 publications receiving 6478 citations. Previous affiliations of Cheng-Wen Wu include National Taiwan University & Global Unichip Corporation.
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Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Journal ArticleDOI
RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme
Ching-Yi Chen,Hsiu Chuan Shih,Cheng-Wen Wu,Chih He Lin,Pi-Feng Chiu,Shyh Shyuan Sheu,Frederick T. Chen +6 more
TL;DR: This paper proposes defect and fault models specific to RRAM, i.e., the Over-Forming (OF) defect and the Read-One-Disturb (R1D) fault, and develops a novel squeeze-search scheme to identify the OF defect, which leads to the Stuck-At Fault (SAF).
Journal ArticleDOI
Built-in redundancy analysis for memory yield improvement
TL;DR: Three redundancy analysis algorithms which can be implemented on-chip based on the local-bitmap idea are presented: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate.
Proceedings ArticleDOI
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
TL;DR: A novel testing scheme for TSVs in a 3D IC is presented by performing on-chip TSV monitoring before bonding, using a sense amplification technique that is commonly seen on a DRAM.