Showing papers by "Chenming Hu published in 1983"
01 Dec 1983
TL;DR: In this paper, the physics of several hot-electron currents and their impact on IC performance and reliability are reviewed, and the authors emphasize the driving force of all hotelectron effects.
Abstract: The physics of several hot-electron currents and their impact on IC performance and reliability is reviewed, V_{d} - V_{dsat} is emphasized as the driving force of all hot-electron effects. V_{g}, V_{sub} , and L affect the hot-electron effects only through their influence on V dsat . A simple hot-electron sealing rule is to scale V_{d}, V_{t} , and \sqrt{x_{ox}x_{j}} in proportion to L . Several proposed structural changes should provide considerable relief to the hot-electron problem.
100 citations
TL;DR: In this paper, the behavior of hot-electron gate and substrate currents in very short channel devices was studied and an empirical relationship between the effective electron temperature and the field was found to be T e = 9.05 × 10-3E.
Abstract: The behaviors of the hot-electron gate and substrate currents in very short channel devices were studied. For a test device with electrical channel length of 0.14 µm, the hot-electron substrate current can be detected at 0.9-V drain voltage which is lower than the silicon band gap. The gate current can be measured at 2.35-V drain voltage, which is lower than the oxide-silicon energy barrier for electrons. These measurements support the quasi-thermal-equilibrium approximation and suggest that the hot-electron-induced problems cannot be eliminated in future VLSI MOSFET's of arbitrarily short channels by reducing the drain bias below some constant critical energies. An empirical relationship between the effective electron temperature and the field is found to be T e = 9.05 × 10-3E.
74 citations
TL;DR: Light emission from Si MOSFETs operating in the saturation region is observed in this article, which provides direct evidence for the phenomenon of photocarrier generation in the substrate of VLSI's.
Abstract: Light emission from Si MOSFET's operating in the saturation region is observed. This observation provides direct evidence for the phenomenon of photocarrier generation in the substrate of VLSI's. The light emission appears to be uniform along the device width and emanates from the drain end of the MOSFET under normal operation. Light spots of much higher intensity are observed when the device is biased into the snap-back regime. This provides insights into the mechanism of snap-back breakdown.
42 citations
TL;DR: In this article, a model for the drain I-V characteristics is proposed and a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation.
Abstract: When a short-channel MOSFET is driven into the avalanche-induced breakdown region, the drain current increases rapidly and usually shows a snapback characteristic. Both the substrate current and the current collected by a nearby reverse-biased p-n junction also increases with increasing drain current in this region of operation. All of these effects are associated with minority-carrier injection from the source junction into the substrate. A model for the drain I-V characteristics is proposed. Also presented is a related model incorporating conductivity modulation that predicts linear relationships between the substrate and the collection currents and the drain current in this region of operation. Experimental results agree well with the models.
37 citations
TL;DR: In this article, the authors present a quantitative model for tunneling-induced electron-hole pair generation on p-type and n-type substrate MOS capacitors, except for those with ultrathin oxides.
Abstract: Deep depletion in both p-type and n-type substrates can be induced by minority carriers tunneling away from the substrate. When this occurs, tunneling current becomes saturated at the rate of carrier generation in the substrate, with the excess applied voltage dropped across the deep-depletion region. We present a quantitative model for this phenomenon based on balancing the tunneling current and the space-charge generation current. Conversely, the usual transient deep depletion in n-type substrate MOS capacitors can be terminated by tunneling-induced electron-hole pair generation, except for those with ultrathin oxides (<40 A).
36 citations
TL;DR: In this article, a simple model is proposed to calculate the low-level punchthrough characteristics, taking into account the two-dimensional geometrical effects, and the model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters and the gate, drain, and substrate bias.
Abstract: Punchthrough currents impose severe limitations on the minimum channel length and leakage currents of scaled MOS transistors. A simple model is proposed to calculate the low-level punchthrough characteristics. Taking into account the two-dimensional geometrical effects, this model calculates the drain-induced barrier-lowering (DIBL) and the punchthrough current as a function of the processing parameters, and the gate, drain, and substrate bias. Experiments on devices with substrate dopings 6 × 1014and 6.6 × 1015cm-3and channel lengths from 1 to 2 µm show good agreement with the theory.
25 citations
TL;DR: In this article, a model for dV/dt breakdown in power MOSFET's is proposed, which allows quantitative analysis of the DV/dt limitation of MOS-FET circuits.
Abstract: A model for dV/dt breakdown in power MOSFET's is proposed. This model allows quantitative analysis of dV/dt limitation in power MOSFET circuits. Experimental results show good agreement with theoretical predictions.
17 citations
01 Dec 1983
TL;DR: In this article, the degradation of thin gate oxide (∼100A) n and p-channel MOSFETs subjected to the substrate hot carrier injection is discussed.
Abstract: The degradation of thin gate oxide (∼100A) n and p-channel MOSFETs subjected to the substrate hot carrier injection is discussed. The generation of oxide trapped charges is observed to be sublinearly dependent on the applied oxide field, while the generation of interface trapped charges shows a linear dependence on the applied oxide field. The generation rates are found to be a function of carrier fluence and the oxide field, and are independent of the injection current density. The generation of interface traps correlates well with the mobility and subthreshold current degradation. An oxide field around 5MV/cm is found to be a critical value for accelerating device degradation. There is no significant interface trap generation under substrate hot hole injection for the hole fluence up to 2\times10^{17} /cm2. The threshold voltage shifts decrease with increasing applied substrate bias. Possible mechanisms are discussed to account for the experimental data.
15 citations
01 Dec 1983
TL;DR: In this paper, theoretical modeling and experimental results on direct tunneling, tunneling-induced electron-hole pair generation in silicon, and hole tunneling are presented, which not only lead us to better understand the fundamental limits in these devices but also provide us with some insights in the physical properties of the Si-Si02 materials.
Abstract: all relevant effects associated with charge tunneling through thin oxide in the MOS system. In particular, we need to understand the tunneling characteristics of thin oxides so that these devices are scaled properly without suffering performance penalty. In this paper, theoretical modeling and experimental results on direct tunneling, tunnelinginduced electron-hole pair generation in silicon, and hole tunneling are presented. These studies not only lead us to better understand the fundamental limits in these devices but also provide us with some insights in the physical properties of the Si-Si02 materials.
10 citations
TL;DR: In this article, the I-V characteristics of power MOS transistors in the reverse mode were discussed and the theory for device operation in the normal mode was extended to cover three regions of operation in reverse mode.
Abstract: Power MOSFET's may be used to obtain a low voltage drop in a rectifier circuit This function will grow more important in future low voltage power supplies In such a circuit, the MOSFET must operate in the "reverse mode," in the sense that the current flow is opposite to the conventional direction This paper discusses the I-V characteristics of power MOS transistors in the reverse mode by extending the theory for device operation in the normal mode Three regions of operation in the reverse mode are identified Calculated I-V curves compare favorably with the measured curves of a commercial power MOSFET
10 citations
01 Jan 1983
TL;DR: In this paper, an evaluation of measured linear and power-law relationships among the channel, substrate and minority-carrier currents is presented to simplify the visualizing, testing and modeling of hot-electron currents.
Abstract: An evaluation of measured linear and power-law relationships among the channel, substrate and minority-carrier currents, will be reported The results simplify the visualizing, testing and modeling of hot-electron currents that affect IC performance and reliability
Abstract: Formation of buried p-type and n-type layers in (100) silicon has been accomplished by implanting with 4 MeV boron and 11 MeV arsenic ions respectively. The projected range (Rp) of 4 MeV boron is 5.2 microns with a straggle (ΔRp) of.2 microns. The 11 MeV arsenic implant has a Rp of 4.37 microns with a ΔRp of.37 microns. The 4 MeV boron implant was carried out to a dose of l×1015/ cm2 while the 11 MeV arsenic implant dose was 1.9×1015/ cm2. For both dopants the target holder could be cooled with either liquid nitrogen (LN) or flowing room temperature water (RT). Buried amorphous regions are seen by cross sectional transmission electron microscopy (XTEM) for both boron and arsenic when LN cooling is used. Arsenic shows a buried amorphous region for the RT case as well. The extent of the buried amorphous regions are compared with the energy deposited into nuclear stopping as determined by computer simulation. Threshold levels are determined for the creation of these buried amorphous regions. The boron samples were annealed for 30 minutes at 900°C in a nitrogen ambient, and XTEM shows no residual damage for both cooling conditions. The arsenic samples underwent a two step annealing procedure; 545°C for 16 hours followed by a 945°C step for 15 minutes. Regions containing dislocation networks are observed by XTEM for both cooling conditions. The 4 MeV implanted boron buried layer was applied to an NMOS process. Transistors fabricated above the p-type buried layer show channel mobility, threshold voltage, and sub-threshold leakage which are indistinguishable from transistors fabricated without the buried layer. Vertical npn bipolar transistors have been fabricated using the 11 MeV arsenic buried layer to form the collector. Electrical characteristics from both these devices indicate that megavolt ion implantation can be applied to silicon for active device geometries.
TL;DR: In this article, the authors compare the collection of α-particle generated charge by collectors surrounded by either uniform reflecting or uniform absorbing surfaces as to two extreme cases of any real condition in IC's.
Abstract: We compare the collection of α-particle generated charge by collectors surrounded by either uniform reflecting or uniform absorbing surfaces as to two extreme cases of any real condition in IC's. The comparison for varying α-particle energies and collector sizes indicates that the differences in collected charge for the two cases is less than a factor of two if the α-particle strike is through the center of the collector. We show that the variation of collected charge with feature length is approximately linear in both cases. The effect of scaling on soft errors in static RAM's is discussed. It is assumed that the charge transport is by diffusion only.