Showing papers by "Chenming Hu published in 1985"

Hot-electron-induced MOSFET degradation—Model, monitor, and improvement

Abstract: Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with physical model involving the breaking of the ≡ Si s H bonds. The device lifetime τ is proportional to I_{sub}^{-2.9}I_{d}^{1.9}\Delta V_{t}^{1.5} . If I sub is large because of small L or large V d , etc., τ will be small. I sub (and possibly light emission) is thus a powerful predictor of τ. The proportionality constant has been found to vary by a factor of 100 for different technologies, offering hope for substantially better reliability through future improvements in dielectric /interface technologies. A simple physical model can relate the channel field E m to all the device parameters and bias voltages. Its use in interpreting and guiding hot-electron scaling are described. LDD structures can reduce E m and I sub and, when properly designed, reduce device degradation.

Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement

Abstract: Evidence suggests that MOSFET degradation is due to interface-states generation by electrons having 3.7 eV and higher energies. This critical energy and the observed time dependence is explained with a physical model involving the breaking of the = Si/sub s/H bonds. The device lifetime /spl tau/ is proportional to...

Electrical breakdown in thin gate and tunneling oxides

Abstract: The breakdown of thin oxides (7.9-32 nm) subjected to high-field current injection is investigated in this study. The physical mechanism of breakdown is found to be localized field enhancement at the cathode interface due to hole trapping. The source of this hole trapping is believed to be impact ionization in the SiO 2 . A quantitative model for oxide breakdown based on impact ionization and hole trapping at the cathode is presented and shown to agree well with the experimental J - t and time-to-breakdown, (t BD ) results. We observe that log t BD varies linearly with 1/ E rather than with E as commonly assumed. The field acceleration factor, i.e., the slope of the log t BD versus 1/ E plot, is approximately 140 decades per centimeter per megavolt for the 7.9 nm oxide, with approximately 25 percent of this coming from the field dependence of the impact ionization coefficient and the remainder from the Fowler-Nordheim current dependence on 1/ E . Based on this model, oxide wearout performance might be improved by process changes that reduce interface hole trapping, such as radiation-hard processing, in addition to the reduction of particulate contamination and crystal defects.

Electrical Breakdown in Thin Gate and Tunneling Oxides

Abstract: The breakdown of thin oxides (7.9-32 nm) subjected to high-field current injection is investigated in this study. The physical mechanism of breakdown is found to be localized field enhancement at the cathode interface due to hole trapping. The source of this hole trapping is believed to be impact ionization in the SiO/sub 2/. A quantitative model for oxide breakdown based on impact ionization and hole trapping at the cathode is presented and shown to agree well with the experimental J - t and time-to-breakdown, (t/sub BD/) results. We observe that log t/sub BD/ varies linearly with 1/E rather than with E as commonly assumed. The field acceleration factor, i.e., the slope of the log t/sub BD/ versus 1/E plot, is approximately 140 decades per centimeter per megavolt for the 7.9 nm oxide, with approximately 25 percent of this coming from the field dependence of the impact ionization coefficient and the remainder from the Fowler-Nordheim current dependence on 1/E. Based on this model, oxide wearout performance might be improved by process changes that reduce interface hole trapping, such as radiation-hard processing, in addition to the reduction of particulate contamination and crystal defects.

Quantum yield of electron impact ionization in silicon

Abstract: p‐channel Si‐gate metal‐oxide‐semiconductor transistors of very thin oxides are used for the study of quantum yield of electron impact ionization in silicon. Electrons are injected into silicon from the polysilicon gate by tunneling to give an approximate δ‐function energy distribution. This energy distribution is preserved when electrons pass through the oxide by direct tunneling. Using the carrier‐separation properties of the induced junction, we are able to experimentally measure the number of generated electron‐hole pairs as a function of the incident electron energy, up to 5 eV. Our results are found to be in excellent agreement with recent theoretical calculations of quantum yield. Beyond 5 eV, the interpretations on the experimental data are difficult due to the broadening of the incident electron energy distribution. This broadening effect is caused by strong scattering in the oxide when electrons tunnel by the Fowler–Nordheim (F–N) process. It is observed that the average energy of those electron...

Dependence of channel electric field on device scaling

Abstract: It has been shown previously that the maximum channel electric field E m in a MOSFET is the most important parameter relating to all hot-electron effects and that E m can be represented as ( V_{DS} - V_{DSAT})/l , where l may be regarded as the effective length of the velocity-saturation region. The dependence of l on device geometries and process parameters is investigated in this letter. From both experiment and two-dimensional (2-D) simulation, it is found that E m has a form of ( V_{DS} - V_{DSAT})/ 0.22T\min{ox}\max{1/3}X\min{j}\max{1/2} . Channel length affects the saturation voltage, thus influencing the maximum channel electric field. The scaling of oxide thickness and junction depth, however, often has even greater effects on channel field. This semiempirical model of E m agrees with E m deduced from I SUB within about 5 percent; it can predict I SUB , which has been empirically correlated with hot-electron degradations.

Modeling the turn-off characteristics of the bipolar-MOS transistor

Abstract: Since the turn-off speed of the new bipolar-MOS power transistor is slow compared to that of a MOSFET, it is important to understand the limiting mechanism and the prospect for future improvement. In this letter, it is demonstrated that the turnoff waveform can be explained by a model based on a simple equivalent circuit and the transistor open-base turn-off process. The model is applied to explore the impact of some process modifications on speed improvement and to study the tradeoff between speed and on-resistance.

Thin oxide reliability

Abstract: Dielectric breakdown and oxide and interface charge trapping set the scaling limits for thin oxides. Oxide leakage is far from being the limit. Dielectric breakdown is modeled by hole trapping at "weak" sites with local, above-average current density or large hole trap density. This model predicts a linear relationship between in t BD and 1/F rather than E. It provides a framework for predicting oxide reliability as a function of area and stress condition from limited data. Using this model and the field experience of thin-oxide EEPROM, it is estimated that 0.01% failure per thousand hour is achievable with 9.5 nm oxides at 5V. This is adequate for 1M-bit DRAMs. Charge trapping and interface trap generation sets slightly less restrictive limit for gate oxides. "Defect" reduction holds promise for improving oxide reliability. New dielectrics will probably be necessary at 4M-bit level unless 10 µm2capacitors are available or cell operation is changed. 6.5 nm oxide should be acceptable for 3.3V operation. Again EEPROMs will provide the real-life test for production thin oxide at that thickness.

Floating well CMOS and latchup

Abstract: The operation of CMOS devices in an electrically floating well is considered. The impetus for this study is the potential reduction of silicon area consumption and wiring complexity attainable when the need for well contacts is eliminated. Experimental P-channel transistor characteristics are presented, for both the floating and non-floating well cases; consideration extends to FET device characteristics, subthreshold behavior, as well as junction leakage and breakdown voltage. Results indicate that transistor operation is not significantly affected when the well is electrically floated. Latchup hardness is somewhat but not excessively degraded when the well is floated, and is explained by means of a simple holding voltage model. It is shown that increased source (emitter) resistance may offset this degradation.

Reaction Kinetics, Stress And Microstructure In Titanium-Copper-Titanium Thin Films

Abstract: Interdiffusion, reactions and microstructure in Ti-Cu-Ti trilayer thin films deposited on silicon wafers have been investigated by Rutherford backscattering, and cross-sectional TEM techniques in the temperature range of 350 to 500 °C. The formation of intcrmetallic compounds was found to be symmetric at both interfaces in Ti-Cu-Ti film package. TiCu compound formed first at low temperature and was followed by TiCu3 at higher temperatures. The stress in Ti-Cu film has also been measured in-situ as functions of both temperature and annealing time by thin fused quartz bending-cantilever beam technique. The stress in metallic Ti-Cu film couple on fused quartz was tensile. The stress increased as both annealing time and temperature increased and followed a parabolic relationship with time due to the growth of the intermetallic compound TiCu3. It was possible to calculate stress in the TiCu3 layer from the changes of stress in the bilayer thin film. The stress in TiCu3 was computed to be at about 3 times larger than the stress in the unreacted Ti-Cu thin film couple.