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Showing papers by "Chenming Hu published in 1987"


Proceedings ArticleDOI
01 Dec 1987
TL;DR: In this article, the gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage, due to the band-to-band tunneling occurring in the deep-depletion layer in the gateto-drain overlap region.
Abstract: Significant gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage. This current is found to be due to the band-to-band tunneling occurring in the deep-depletion layer in the gate-to-drain overlap region. In order to limit the leakage current to 0.1pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 1.9MV/cm. This may set another constraint for the power supply voltage and/or oxide thickness in VLSI MOSFET scaling Device design considerations for minimizing the gate-induced drain leakage current are discussed.

338 citations


Journal ArticleDOI
TL;DR: In this paper, it is shown that after holes are injected and trapped in silicon dioxide (SiO2), subsequent electron injection will generate neutral electron traps, which is consistent with the higher trap generation rate in irradiated SiO2.
Abstract: It is shown that after holes are injected and trapped in silicon dioxide (SiO2), subsequent electron injection will generate neutral electron traps. The density of electron traps generated is about 30% of the density of trapped holes. It is proposed that electron traps are created by the energy released through the recombination of electrons and holes, and that this is the mechanism of electron‐trap generation during high‐field oxide stressing. Similar oxide field and thickness dependencies of the rate of electron‐trap generation and hole generation further support this model. This model can reconcile the main evidence for the electron‐trapping oxide breakdown model with the hole‐trapping breakdown model. It is consistent with the higher trap generation rate in irradiated SiO2. An analytical trapping model is derived and the electron capture cross sections of trapped holes and the generated neutral traps are found to be 10−14 cm2 and 5×10−16 cm2, respectively.

129 citations


Journal ArticleDOI
01 Jan 1987
TL;DR: An easily manufacturable 128 K flash EEPROM (electrically erasable programmable read-only memory) was developed based on a novel cell which ensures selflimited erasing, reduces leakage, and increases the cell current.
Abstract: An easily manufacturable 128 K flash EEPROM (electrically erasable programmable read-only memory) was developed based on a novel cell. Programming is achieved through hot-electron injection and erasing through electron tunneling from the floating gate to the drain. The cell is 20% larger than an EPROM cell and contains an integral series transistor which ensures selflimited erasing, reduces leakage, and increases the cell current. The flash EEPROM device can withstand thousands of program/erase cycles. Endurance failures are due to threshold window closing caused by electron trapping in the gate oxide. Typical erasure time is 1 s to clear the entire memory.

92 citations


Journal ArticleDOI
TL;DR: In this paper, the effects of gate and drain voltage waveforms on hot-carrier-induced MOSFET degradation were studied and it was shown that only the falling edge of the gate pulse in the presence of a high drain voltage enhances the degradation rate.
Abstract: The effects of gate and drain voltage waveforms on the hot-carrier-induced MOSFET degradation are studied. Drain votage transients have little effect on the degradation rate. Only the falling edge of the gate pulse in the presence of a high drain voltage enhances the degradation rate. For devices in typical inverter circuits, dc stress results together with the substrate current waveform can predict the degradation rate under ac stress for a wide range of rise and delay times.

70 citations


Journal ArticleDOI
TL;DR: In this paper, the authors reported that the electric field acceleration factor β is not a constant but proportional to E √ minox √ max{-2}, which is the main cause of the wide divergence of β values reported in the literature.
Abstract: Electric-field acceleration factor β is the slope of the \log (t_{BD}) versus E ox curve, where t BD is the time to breakdown at oxide field E ox . We report that β is not a constant but proportional to E\min{ox}\max{-2} . This is the main cause of the wide divergence of β values reported in the literature. The reported oxide thickness dependence of β is believed to be a result of the higher electron trap densities in thicker oxides. Oxide lifetime extrapolation using \log (t_{BD}) , or better, \log (Q_{BD}) against 1/E_{ox} plots is more accurate and has a theoretical basis. Highly accelerated oxide testing appears to be feasible especially for very thin oxides.

62 citations


Journal ArticleDOI
TL;DR: In this article, a semi-quantitative model for the lateral channel electric field in LDD MOSFET's has been derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile.
Abstract: A semi-quantitative model for the lateral channel electric field in LDD MOSFET's has been developed. This model is derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile. A field reduction factor and voltage improvement, indicating the effectiveness of an LDD design in reducing the peak channel field, are used to compare LDD structures with, without, and with partial gate/drain overlap. Approximate equations have been derived that show the dependencies of the field reduction factor on bias conditions and process parameters. Plots showing the trade-off between, and the process-dependencies of, the field reduction factor/voltage improvement and the series resistance are presented for the three cases. Structures with gate-drain overlap are found to provide greater field reduction than those without the overlap for the same series resistance introduced. This should be considered when comparing the double-diffused and spacer LDD structures. It is shown that gate-drain offset can cause the rise of channel field and substrate current at large gate voltages. This offset is also found to be responsible for nonsaturation of drain current. The model has also been compared with two-dimensional simulation results.

57 citations


Journal ArticleDOI
TL;DR: In this article, the I-V characteristics have been modeled with a mobility dependence on V GS of the form µn ∞ (1 + η(V GS - V t /T ox )2+ (E/E c ))-1 for 52-A devices.
Abstract: While hot-carrier-induced degradation is aggravated at cryogenic temperature, a very thin gate-oxide (52-A) device can still tolerate a 3-V power-supply voltage at 77 K. Hot-carrier-induced degradation may not be the limiting factor in choosing the power-supply voltage and special drain structures may be necessary for very thin gate MOSFET's even at 77 K. However, mobility reduction at high V G is more severe both at lower temperatures and for thinner oxides. Electron mobility appears to be oxide-thickness-dependent at 77 K. The dependence of the electron mobility on the normal field is so strong that it results in unusual I-V characteristics such as negative transconductance at 77 K for an oxide field above 3 MV/cm. The I--V characteristics have been modeled with a mobility dependence on V GS of the form µn ∞ (1 + η(V GS - V t /T ox )2+ (E/E c ))-1for 52-A devices.

43 citations


Journal ArticleDOI
TL;DR: In this paper, the critical electron energy for device degradation was found to be 3 −6 eV, depending on the oxide electric field, which is 50% higher than those reported elsewhere.
Abstract: While the substrate current is a useful tool for extrapolating metal‐oxide‐semiconductor field‐effect transistor lifetime from accelerated stressing data, the substrate current can vary significantly during a constant‐voltage stress test. We have studied device degradation using a constant‐field method. The critical electron energy for device degradation is found to be 3–6 eV, depending on the oxide electric field. These values are 50% higher than those reported elsewhere.

35 citations


Journal ArticleDOI
TL;DR: In this paper, it was shown that the substrate current characterization method and modeling approach used for n-MOSFET's is also applicable to p-MSFETs and the impact ionization rate extracted for holes was found to be 8 × 106exp (-37 × 106/E), where E is the electric field.
Abstract: It is shown that the substrate current characterization method and modeling approach used for n-MOSFET's is also applicable to p-MOSFET's The impact ionization rate extracted for holes is found to be 8 × 106exp (-37 × 106/E), where E is the electric field Based on our measurement and modeling result, roughly twice the channel electric field is required for p-MOSFET's to generate the same amount of substrate current as n-MOSFET's The hot-carrier-induced breakdown voltage is therefore also about two times larger

27 citations


Journal ArticleDOI
TL;DR: In this article, the effects of nitridation temperature and time on the properties of the thin nitrided oxide films have been examined and analyzed by using a constant current stress, and it was found that the oxide films nitrated at 900°C exhibit much improved total charge to breakdown and interface trap generation.
Abstract: MIS capacitors on n-type silicon substrate with thin oxide films thermally nitrided in NH 3 gas ambient at different temperatures and for different times have been fabricated. The effects of nitridation temperature and time on the properties of the thin nitrided oxide films have been examined and analyzed by using a constant current stress. It is found that the oxide films nitrided at 900°C exhibit much improved total charge to breakdown and interface trap generation if proper nitridation time is used. The superior characteristics of the fabricated nitrided oxide films using the proposed optimum conditions are suitable for existing CMOS/VLSI applications.

26 citations


Journal ArticleDOI
TL;DR: In this article, the characteristics of MOSFET's with different degrees of gate-to-drain overlap are studied and it is found that there exists a critical length of overlap below which the device hot-electron reliability will suffer.
Abstract: The characteristics of MOSFET's with different degrees of gate-to-drain overlap are studied. It is found that there exists a critical length of overlap below which the device hot-electron reliability will suffer. Since a few hundred angstroms change in the overlap length can cause the transition from good to poor reliability, devices designed for minimum gate-to-drain overlap might exhibit grossly nonuniform characteristics as a result of minor variations in the overlap structure across a wafer, such as that due to tilted implant. On the other hand, devices with larger overlap have a higher gate-to-drain/source capacitance. Therefore, there exists only a narrow margin within which an optimal compromise between device performance and characteristics can be achieved. This margin will shrink further as device dimensions are scaled down.

Journal ArticleDOI
TL;DR: In this paper, a method is described which uses accurate measurement of gate-to-drain/source overlap capacitances to determine the gate to source overlap length for process control as well as device characterization.
Abstract: A method is described which uses accurate measurement of gate-to-drain/source overlap capacitances to determine the gate-to-drain/ source overlap length for process control as well as device characterization. The method might also be a useful analytical tool in studying lateral dopant diffusion. Using this technique, the variation in overlap length of MOSFET's in a 4-in wafer is mapped. It is found that a significant spread of the overlap exits and is attributable to the implant shadowing by the polysilicon gate.

Journal ArticleDOI
TL;DR: In this article, the effect of the gate material on the breakdown characteristics of ultra-thin silicon dioxide films at low voltages was investigated and the results were interpreted in terms of a simple model of hole tunneling resulting from hot-hole generation in the anode by hot electrons entering from the silicon dioxide.
Abstract: In this work we investigate the effect of the gate material on the breakdown characteristics of ultra-thin silicon dioxide films at low voltages (<6 V). When MOS capacitors are stressed with a positive gate voltage, the charge to breakdown and time to breakdown at a fixed oxide-voltage drop are significantly smaller in p+ polysilicon-gate capacitors than in n+ polysilicon-gate capacitors. The results are interpreted in terms of a simple model of hole tunneling resulting from hot-hole generation in the anode by hot electrons entering from the silicon dioxide. Extrapolation of high-voltage-breakdown lifetime measurements for relatively thick-oxide devices to low voltages may be complicated by this mechanism.

Proceedings Article
22 May 1987
TL;DR: In this article, the authors used the degradation of drain current to estimate the lifetime of hot-carrier-induced MOSI FT degradation in VLSI technology development and showed that a reasonable fit is lifetime ≈ 106 [ISUB/W]−3.
Abstract: Hot-carrier induced MOSi FT degradation is a serious concern to VLSI technology development. The substrate current has been shwon to be a good monitor of hot-carrier population and can be used to extrapolate the accelerated stressing results to normal-voltage lifetime. As illustrated in Fig. 1. lifetime projection under DC stressing conditions is thus well established. Fig, 1 includes data reported in the literature[1,2] as well as measurements performed in our laboratory. Not only is there a common slope (≈3) for devices from different sources, but the magnitude fall in a narrow range for most devices. A reasonable fit is lifetime ≈ 106 [ISUB/W]−3. The lifetimes in Fig. 1 were defined at 10 mV shift of the threshold voltage VT. The degradation of drain current Id is also commonly used for lifetime definition. Fig. 2 shows that under DC stress, ΔVT=10 mV corresponds to ΔId/Id=3 % for wide range of biases and device dimensions.

Journal ArticleDOI
TL;DR: The impetus for this study is the potential reduction of silicon area consumption and wiring complexity involved in contacting the well diffusion, and results indicate that an electrically floating well does not seem to have significant adverse effects on transistor operation.
Abstract: The operation of CMOS devices in an electrically floating well is considered. The impetus for this study is the potential reduction of silicon area consumption and wiring complexity involved in contacting the well diffusion. Theoretical expectations for device behavior are presented and corroborated with experimental data; consideration extends to PMOSFET device characteristics, subthreshold behavior, as well as junction leakage and breakdown voltage. Examination of n-channel devices, in p-wells, indicates that these are more susceptible to floating well effects, as expected. The primary changes in device behavior include generation of substrate current, slight increase in leakage currents, and some degradation in latchup holding voltage. Results indicate that an electrically floating well does not seem to have significant adverse effects on transistor operation.

Proceedings ArticleDOI
01 Jan 1987
TL;DR: In this article, a substrate current model and a quasi-static hot-electron-induced MOSFET degradation model have been implemented in the Substrate Current and Lifetime Evaluator (SCALE).
Abstract: A substrate current model and a quasi-static hot-electron-induced MOSFET degradation model have been implemented in the Substrate Current and Lifetime Evaluator (SCALE). It is shown that quasi-static simulation is valid for a class of waveforms including those encountered in inverter-based logic circuits. The validity and limitations of the model are illustrated with experimental results. SCALE is linked to SPICE externally in a pre- and post- processors fashion to form an independent simulator. The pre-processor interprets the input deck, and requests SPICE to output the transient node voltages of the user-selected devices. The post-processor then calculates the transient substrate current and makes lifetime prediction.

Proceedings ArticleDOI
01 Dec 1987
TL;DR: An analytic non-quasistatic (NQS) MOSFET model has been derived and implemented in SPICE as discussed by the authors, which is based on an approximate solution to the non-linear transient current continuity equation in the channel.
Abstract: An analytic non-quasistatic(NQS) MOSFET model has been derived and implemented in SPICE It is based on an approximate solution to the non-linear transient current continuity equation in the channel The model includes the large signal transient and the small signal frequency response analyses Comparisons have been made between this model and the 1-D numerical solution to the current continuity equation, 2-D device simulation(PISCES) and the quasistatic(QS) results The channel charge partitioning scheme in the charge based model is shown to be inadequate for the fast transient and the high frequency AC analysis This model does not use a charge partitioning scheme and the currents are dependent on the history of the terminal voltages, not just the instantaneous voltages and their derivatives

Proceedings Article
22 May 1987
TL;DR: In this paper, the process and characteristics of submicron MOSFETs fabricated with tungsten gate on 10 nm gate oxide and self-aligned TiSi on source-drain regions were investigated.
Abstract: Tungsten is an attractive alternative to n+ poly for submicron CMOS gate due to its near midgap work function (⋍4.8 eV) and low resistivity (⋍ 10 μΩ-cm), The midgap work function results in desired threshold voltages (± 0.6V) without the need for channel implant into n or p-channel devices. This avoids the inferior buried-channel operation of PMOS and, at the same time yields a higher mobility and transconductance for NMOS. Tungsten gate FET's with 20 nm gate oxide have been reported previously1. This paper reports, for the first time, process and characteristics of submicron MOSFET's fabricated with tungsten gate on 10 nm gate oxide and self-aligned TiSi; on source-drain regions. It is demonstrated that tungsten gate is stable on such a thin oxide and 35% higher inversion layer electron mobility (compared with n+ poly gate) is obtained due to a factor of three reduction in the transverse field at the interface. Key technology issues have been investigated.

Journal ArticleDOI
Rajesh Gupta1, I. Sakai, Chenming Hu
TL;DR: It is shown that there may exist a certain optimum epitaxial layer thickness that leads to a maximum latchup holding voltage and that even a shallow trench is remarkably effective in raising the holding voltage.
Abstract: We suggest a method to estimate the effects of substrate resistances on the latchup holding voltage of CMOS integrated circuits. The estimated holding voltages are shown to be in reasonable agreement with the experimental data inspite of two bold approximations. Using this method, we analyze the effect of several variables relating to the epitaxial substrate and/or the well-isolation trench on the latchup holding voltage. It is shown that there may exist a certain optimum epitaxial layer thickness that leads to a maximum latchup holding voltage and that even a shallow trench is remarkably effective in raising the holding voltage. Physical explanations are offered for the effects of the epitaxial layer and trench on the holding voltage. Examples are presented to illustrate the general effects of several design variables and to aid the design and interpretation of process experiments.


Proceedings ArticleDOI
01 Dec 1987
TL;DR: In this paper, the performance and hot-electron reliability of submicron n-channel MOSFET's is investigated. But, the results suggest that the basic physics is rather well-understood and the design criteria developed for micron-size devices can be extended to cover their deep-submicron counterparts.
Abstract: A study of the performance and hot-electron reliability of submicron n-channel MOSFET's is presented. Well-established hot-electron-based physical models are adequate in explaining the general behaviors of the drain, substrate, and gate currents of these devices. These results suggest that the basic physics is rather well-understood and the design criteria developed for micron-size devices can be extended to cover their deep-submicron counterparts. Hot-electron studies reveal a channel-length dependence in device degradation. This phenomenon together with gate-induced drain leakage current [1] will impose an upper limit on the supply voltage and a lower limit on the gate oxide thickness. Based on device degradation results alone, the power supply voltage for a quarter-micron device with oxide thickness of 86 A should be limited to 2.5 V if no degradation-resistant structure is used.

Journal ArticleDOI
TL;DR: In this paper, a new charge transport and trapping model for scaled nitride-oxide stacked films is evolved from the experimental observations, which can be thought of as an oxide film with electron trapping at the nitride/oxide interface.

Proceedings Article
22 May 1987
TL;DR: In this article, the authors used log(tBD) or better log(QBD) against 1/Eox plot to extrapolate the oxide lifetime of defect-related break-down.
Abstract: Oxide lifetime extrapolation using log(tBD) or better log(QBD) against 1/ Eox plot is more accurate and has a theoretical basis. Highly accelerated oxide test completed in seconds appears to be feasible. The acceleration factor is also a function of the severity of the oxide defect. Extrapolation of defect-related break-down lifetime can be performed assuming an effective oxide thinning for defects.

Journal ArticleDOI
TL;DR: The operating characteristics of MOS transistors constructed in substrates subject to MeV ion implantation have been studied in this article, where a standard CMOS process was modified to include high-energy implantation in order to produce a buried layer for device isolation.
Abstract: The operating characteristics of MOS transistors constructed in substrates subject to MeV ion implantation have been studied. A standard CMOS process was modified to include high-energy implantation in order to produce a buried layer for device isolation. The process included various high energy implant energies and CMOS well depths. It was seen that device behavior of MOSFETs in the substrate were virtually unaffected by the MeV implantation; channel surface mobility, transconductance and threshold voltage were unchanged. Some variations in body effect parameter and output resistance were noted. Further studies of the CMOS well behavior indicated an increase in well/substrate leakage currents as MeV implanted buried-layer depths decreased.